1 Panel: The Electronics Industry Supply Chain: Who Will Do What?
2 Nanometer Futures
3 System-Level Configurability: Bus, Interface, and Processor Design
4 Making Verification More Efficient
5 SoC and High-Level DFT
6 Panel: The Next HDL: If C++ is the Answer, What was the Question?
7 Design for Subwavelength Manufacturability: Impact on EDA
8 New Ideas in Logic Synthesis
9 Analog Design and Modeling
10 Scan-Based Testing
11 Panel: Your Core - My Problem: Integration and Verification of IP
12 Configurable Computing: Reconfiguring the Industry
13 Interconnect Design Optimization
14 Power Estimation Techniques
15 Functional Validation Based on Boolean Reasoning (BDD, SAT)
16 Verification: Life Beyond Algorithms
17 Dissecting an Embedded System: Lessons from Bluetooth
18 Algorithmic and Compiler Transformations for High-Level Synthesis
19 Gate Delay Calculation
20 Memory, Bus and Current Testing
21 Panel: (When) Will FPGAs Kill ASIC's?
22 Inductance 101 and Beyond
23 Memory Optimization Techniques for DSP Processors
24 Technology Dependant Logic Synthesis
25 Collaborative and Distributed Design Frameworks
26 Panel: When Will the Analog Design Flow Catch Up With the Digital Methodology?
27 Closing the Gap Between ASIC and Custom: Design Examples
28 Energy and Flexibility Driven Scheduling
29 Representation and Optimization for Digital Arithmetic Circuits
30 Techniques for IP Protection
31 Visualization and Animation for VLSI Design
32 Application-Specific Customization for Systems-on-a-Chip
33 Satisfiability Solvers and Techniques
34 Power and Interconnect Analysis
35 Domain Specific Design Methodologies
36 Panel: Debate: Who Has Nanometer Design Under Control?
37 Analysis and Implementation for Embedded Systems
38 Industrial Case Study in Verification
39 Integrated High-Level Synthesis Based Solutions
40 Timing Verification and Simulation
41 On-Chip Communication Architectures
42 Compiler and Architecture Interactions
43 Timing with Crosstalk
44 Low Power Design: Systems to Interconnect
45 Floorplanning Representations and Placement Algorithms
46 Panel: What Drives EDA Innovation?
47 Signal Integrity: Avoidance and Test Techniques
48 Novel Approaches to Microprocessor Design and Verification
49 Scheduling Techniques for Power Management
50 Novel Devices and Yield Optimization

Plenary Panel Panel: Embedded System Design: The Real Story

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