A design competition open to full-time
graduate and undergraduate students at universities and colleges.

    The purpose of the Student Design Contest is to promote excellence in the design of electronic systems by providing competition between graduate and undergraduate students at universities and colleges.

DESIGN CONTEST WINNERS

OPERATIONAL CATEGORY
1st Place $4,000
(session 44.5) A True Single-Phase 8-bit Adiabatic Multiplier
Suhwan Kim,Conrad H. Ziesler, Marios C. Papaefthymiou - Univ. of Michigan
2nd Place $2,500
(session 9.1) Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication
Jafar Savoj, Behzad Razavi - Univ. of California, Los Angeles
2nd Place $2,500
Optimal Design of a Low Power, Low Noise 3.4 GHz CMOS Downconverter
Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Willy Sansen - Katholieke Univ., Leuven, Belgium

CONCEPTUAL CATEGORY
1st Place $4,000, Best Paper $1,000
(session 50.2) Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications
Seungbae Lee, Gijoon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake - Univ. of Michigan
2nd Place $2,500
A Configurable, Algorithm-Specific Processor for Real-Time Wavelet-Based Video
Li Ding, Yi Li, Richard B. Brown - Univ. of Michigan 3rd Place $1,500
VLSI Implementation of Binaural Spatializer Using FIR Head-Related Transfer Function (HRTF)
NamSung Kim, Jiyoun Kim, Mingyu Cho, TaeYoung Choi, Trevor Mudge ­ Univ. of Michigan

HONORABLE MENTIONS $500
A 1.8 GHz CMOS Cellular Transceiver Front-End: From Integrated Circuit to Integrated System Design
Michiel Steyaert, Bram De Muer, Johan Janssens, Marc Borremans - Katholieke Univ., Leuven, Belgium
HiPAR-DSP 16: VLSI-Design of a Second Generation Programmable Parallel Multimedia-DSP
Willm Hinrichs, Jens Peter Wittenburg, Hanno Lieske, Helge Kloos, Lars Friebe, Peter Pirsch - Univ. of Hannover, Germany

2001 Participants Sites True Single-Phase Adiabatic Multiplier A Configurable, Algorithm-Specific Processor for Real-Time Wavelet-Based Video HiPAR-DSP16: VLSI-Design of a Second Generation Programmable Parallel Multimedia-DSP Increased Bandwidth for 3-D Neural Recording Arrays Optimal Design of a Low Power, Low Noise 3.4 GHz CMOS Downconverter A 1.8 GHz CMOS Cellular transceiver front-end Last year's winners include students from seven different universities from around the world.

 

 
   The contest will allow entries of both integrated circuits and electronic systems (board-level design). It will have two categories: 'Conceptual' and 'Operational.'
    Operational designs will have been implemented and tested. Proof of implementation in the form of die- or board-photographs and measurement data must be supplied.
     Conceptual designs need not have been implemented but must have been thoroughly simulated and must include a test plan.

CRITERIA FOR ENTERING THE CONTEST
    Submissions are invited from full-time graduate and undergraduate students. The design must have taken place as part of the students' course or research work at the university and must have been completed within 18 months prior to the submission deadline.
    Submission are made electronically via the DAC web site. Submissions include two files. The first is the title and a 60-word abstract. The second is a document describing the design not exceeding 6000 words, with a recommended length of 4000 words. The deadline for submission was December 15, 2000.
    It will be appropriate for a professor to be included as a co-author if he/she was instrumental in the student(s) approach to the design, or provided other guidance that contributed to the success of the design.
    Submissions are judged by a panel of experts including members of the DAC Technical Program Committee and other representatives from industry. Judging criteria include originality, soundness of engineering, measured performance and the quality of the written submission. Winners will be notified in mid-February.