|
|

| | Wednesday, June 12, 2002, 2:00 PM - 4:00 PM | Room: Auditorium A
|
 |
SESSION 27
|
| | Power Distribution Issues
 |
| | Chair: Sachin Sapatnekar - Univ of Minnesota, Minneapolis, MN
|
| | Organizers: Abhijit Dharchoudhury, Tadahiro Kuroda
|
| | Power distribution issues are becoming extremely important as levels of integration increase. The first paper describes a model-order reduction method for hierarchical power grid analysis. The second paper describes a frequency-domain macromodel for block current signatures. The third paper describes circuit models for the chip interface, and the fourth paper describes a method for analyzing symmetrical P/G networks. The final paper describes a method to optimize clock distribution networks using supply current folding.
|
| | 27.1 |
HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodeling Engine for RLKC Power Delivery
 |
| |  | Speaker(s): | Yahong Cao - Univ. of Wisconsin, Madison, WI
|
| |  | Author(s): | Yahong Cao - Univ. of Wisconsin, Madison, WI
YuMin Lee - Univ. of Wisconsin, Madison, WI
Tsunghao Chen - Univ. of Wisconsin, Madison, WI
ChungPing Chen - Univ. of Wisconsin, Madison, WI
|
| | 27.2 | High-Level Current Macro-Model For Power-Grid Analysis |
| | Speaker(s): | Srinivas Bodapati - Univ. of Illinois, Urbana, IL
|
| | Author(s): | Srinivas Bodapati - Univ. of Illinois, Urbana, IL
Farid N. Najm - Univ. of Toronto, Toronto, ON, Canada
|
| | 27.3 | Macro-Modeling Concepts For The Chip Electrical Interface |
| | Speaker(s): | Claude R. Gauthier - Sun Microsystems, Sunnyvale, CA
|
| | Author(s): | Brian W. Amick - Sun Microsystems, Austin, TX
Claude R. Gauthier - Sun Microsystems, Sunnyvale, CA
Dean Liu - Sun Microsystems, Sunnyvale, CA
|
| | 27.4 | Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks |
| | Speaker(s): | Hui Zheng - Carnegie Mellon Univ., Pittsburgh, PA
|
| | Author(s): | Hui Zheng - Carnegie Mellon Univ., Pittsburgh, PA
Lawrence T. Pileggi - Carnegie Mellon Univ., Pittsburgh, PA
|
| | 27.5 | Clock Tree Optimization in Synchronous CMOS Digital Circuits for Substrate Noise Reduction Using Folding of Supply Current Transients |
| | Speaker(s): | Mustafa Badaroglu - IMEC, Leuven, Belgium
|
| | Author(s): | Mustafa Badaroglu - IMEC, Leuven, Belgium
Kris Tiri - IMEC, Leuven, Belgium
Stephane Donnay - IMEC, Leuven, Belgium
Piet Wambacq - IMEC, Leuven, Belgium
Ingrid Verbauwhede - Univ. of California, Los Angeles, CA
Georges G. Gielen - Katholieke Univ., Leuven, Belgium
Hugo De Man - IMEC, Leuven, Belgium
|
  |
|