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| | Wednesday, June 12, 2002, 4:30 PM - 6:00 PM | Room: 288
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SESSION 34
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| | Design Methodologies Meet Network Applications
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| | Chair: Anand Raghunathan - NEC USA Inc., Princeton, NJ
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| | Organizers: Anand Raghunathan, Marco Di Natale
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| | Networking chips represent a challenging class of applications for EDA tools and methodologies. This session contains presentations that showcase novel design methodologies developed to address performance and power issues in network processors and switch fabrics. The first paper presents an advanced memory management methodology for high-performance network processors. The second presentation addresses power analysis of switch fabrics used in network routers, while the final presentation discusses memory optimizations for single chip switch fabrics.
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| |  34.1 |
System-Level Performance Optimization of the Data Queueing Memory Management in High-Speed Network Processors
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| | | Speaker(s): | Chantal Ykman - IMEC, Leuven, Belgium
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| | | Author(s): | Chantal Ykman - IMEC, Leuven, Belgium
Jurgen Lambrecht - IMEC, Leuven, Belgium
Diederik Verkest - IMEC, Leuven, Belgium
Francky Catthoor - IMEC, Heverlee, Belgium
Aris Nikologiannis - Ellemedia, Athens, Greece
George Konstantoulakis - Inaccess Networks, Athens, Greece
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| | 34.2 |
Analysis of Power Consumption on Switch Fabrics in Network Routers |
| | Speaker(s): | Terry Tao Ye - Stanford Univ., Stanford, CA
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| | Author(s): | Terry Tao Ye - Stanford Univ., Stanford, CA
Luca Benini - Univ. ` di Bologna - DEIS, Bologna, Italy
Giovanni De Micheli - Stanford Univ., Stanford, CA
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| | 34.3 |
Memory Optimization in Single Chip Network Switch Fabrics |
| | Speaker(s): | David J. Whelihan - Carnegie Mellon Univ., Pittsburgh, PA
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| | Author(s): | David J. Whelihan - Carnegie Mellon Univ., Pittsburgh, PA
Herman Schmit - Carnegie Mellon Univ., Pittsburgh, PA
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