Wolfgang Rosenstiel - Univ. of Tubingen, Tubingen, DEU
| | Organizers: Wolfgang Rosenstiel
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| | The first paper will discuss the application of FPV to the validation of the PentiumŪ 4 microarchitecture. New approaches are considered to broaden the application of FV techniques, particularly at higher abstraction levels. GSTE and SAT will significantly increase the scope of what can be formally verified. Second, the verification strategy for the integration of a multi-processors baseband chip for the 3G wireless phone market is presented. Examples and metrics illustrate the key design challenges of large SoC verification, enhancement opportunities are explored. Last, but not least, the development of large servers is facing multiple challenges like mixing design styles from custom VLSI to ASIC and SoC designs, including various IP as well as a combination of hardware and firmware.
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| |  1.1 |
High-Level Formal Verification of Next-Generation Microprocessors
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| | Speaker(s): | Tom Schubert - Intel Corp., Hillsboro, OR
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| | Author(s): | Tom Schubert - Intel Corp., Hillsboro, OR
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| | 1.2 | Verification Strategy for Integrating 3G Baseband SoC |
| | Speaker(s): | Yves Mathys - Motorola, Inc., Geneva, Switzerland
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| | Author(s): | Yves Mathys - Motorola, Inc., Geneva, Switzerland
Andre Chatelain - Motorola, Inc., Geneva, Switzerland
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| | 1.3 | Improvements in Functional Simulation Addressing Challenges in Large, Distributed Industry Projects |
| | Speaker(s): | Klaus-Dieter Schubert - IBM Corp., Boeblingen, Germany
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| | Author(s): | Klaus-Dieter Schubert - IBM Corp., Boeblingen, Germany
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