Tuesday, June 3, 2003, 2:00 PM - 4:00 PM | Room: 209AB

   SESSION 10
  Cyclic and Non-Cyclic Combinational Circuit Synthesis
  Chair: Victor Kravets - IBM Corp., Yorktown Heights, NY
  Organizers: Marek Perkowski, Soha Hassoun

  This session addresses logic minimization. The first paper presents a practical enhancements to recently proposed constructive decomposition. The second paper proposes a new approach to SOP minimization basd on decomposition. The third paper explores novel general cofactoring for for multi-valued functions to speed functional evaluation. The last two papers address combinational optimizations for cyclic circuits.

  10.1   A New Enhanced Constructive Decomposition and Mapping Algorithm
  Speaker(s): Alan Mishchenko - Univ. of California, Berkeley, CA
  Author(s): Alan Mishchenko - Univ. of California, Berkeley, CA
Xinning Wang - Intel Corp., Hillsboro, OR
Timothy Kam - Intel Corp., Hillsboro, OR
  10.2Large-Scale SOP Minimization Using Decomposition and Functional Properties
  Speaker(s): Tsutomu Sasao - Kyushu Institute of Tech., Fukuoka, Japan
  Author(s): Alan Mishchenko - Univ. of California, Berkeley, CA
Tsutomu Sasao - Kyushu Institute of Tech., Fukuoka, Japan
  10.3sGeneralized Cofactoring for Logic Function Evaluation
  Speaker(s): Yunjian Jiang - Univ. of California, Berkeley, CA
  Author(s): Yunjian Jiang - Univ. of California, Berkeley, CA
Slobodan Matic - Univ. of California, Berkeley, CA
Robert K. Brayton - Univ. of California, Berkeley, CA
  10.4sMaking Cyclic Circuits Acyclic
  Speaker(s): Stephen A. Edwards - Columbia Univ., New York, NY
  Author(s): Stephen A. Edwards - Columbia Univ., New York, NY
  10.5The Synthesis of Cyclic Combinational Circuits
  Speaker(s): Marc D. Riedel - Caltech, Pasadena, CA
  Author(s): Marc D. Riedel - Caltech, Pasadena, CA
Jehoshua Bruck - Caltech, Pasadena, CA