Siva Narendra - Intel Corp., Hillsboro, OR
| | Organizers: Renu Mehra
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| | Leakage power consumption is projected to be one of the most dominant power components in very deep-submicron technologies. Papers in this session address different issues related to leakage power estimation and minimization.
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| |  11.1 |
Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling
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| | Speaker(s): | Saibal Mukhopadhyay - Purdue Univ., West Lafayette, IN
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| | Author(s): | Saibal Mukhopadhyay - Purdue Univ., West Lafayette, IN
Arijit Raychowdhury - Purdue Univ., West Lafayette, IN
Kaushik Roy - Purdue Univ., West Lafayette, IN
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| | 11.2 | Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage |
| | Speaker(s): | Dongwoo Lee - Univ. of Michigan, Ann Arbor, MI
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| | Author(s): | Dongwoo Lee - Univ. of Michigan, Ann Arbor, MI
Wesley Kwong - Univ. of Michigan, Ann Arbor, MI
Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI
David Blaauw - Univ. of Michigan, Ann Arbor, MI
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| | 11.3 | Distributed Sleep Transistor Network for Power Reduction |
| | Speaker(s): | Changbo Long - Univ. of Wisconsin, Madison, WI
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| | Author(s): | Changbo Long - Univ. of Wisconsin, Madison, WI
Lei He - Univ. of California, Los Angeles, CA
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| | 11.4s | Implications of Technology Scaling on Leakage Reduction Techniques |
| | Speaker(s): | Yuh-Fang Tsai - Penn State Univ., University Park, PA
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| | Author(s): | Yuh-Fang Tsai - Penn State Univ., University Park, PA
David Duarte - Intel Corp., Portland, OR
Vijaykrishnan N. - Penn State Univ., University Park, PA
Mary J. Irwin - Penn State Univ., University Park, PA
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| | 11.5s | Static Leakage Reduction through Simultaneous Threshold Voltage and State Assignment |
| | Speaker(s): | David Blaauw - Univ. of Michigan, Ann Arbor, MI
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| | Author(s): | Dongwoo Lee - Univ. of Michigan, Ann Arbor, MI
David Blaauw - Univ. of Michigan, Ann Arbor, MI
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