Ralph Otten - Eindhoven Univ. of Tech., Eindhoven, NLD
| | Organizers: C Y Roger Chen, Carl Sechen
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| | Since delay is an increasingly important issue in chip design, emphasis is shifting from area and wire length towards timing. Delay budgeting and retiming have found their place in design trajectory, but integration with placement is very much a topic of today. Also the possibility of logic replication in order to meet timing constraints will be considered in this session. Once the timing requirements can be formulated as constraints on nets, powerful tool combinations can provide high quality placements.
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| |  13.1 |
Timing Optimization of FPGA Placements by Logic Replication
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| | Speaker(s): | Giancarlo Beraudo - Univ. of Illinois, Chicago, IL
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| | Author(s): | Giancarlo Beraudo - Univ. of Illinois, Chicago, IL
John Lillis - Univ. of Illinois, Chicago, IL
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| | 13.2 | Delay Budgeting in Sequential Circuits with Application to FPGA Placement |
| | Speaker(s): | Chao-Yang Yeh - Univ. of California, Santa Barbara, CA
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| | Author(s): | Chao-Yang Yeh - Univ. of California, Santa Barbara, CA
Malgorzata Marek-Sadowska - Univ. of California, Santa Barbara, CA
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| | 13.3 | Multilevel Global Placement with Retiming |
| | Speaker(s): | Xin Yuan - Univ. of California, Los Angeles, CA
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| | Author(s): | Jason Cong - Univ. of California, Los Angeles, CA
Xin Yuan - Univ. of California, Los Angeles, CA
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| | 13.4 | Force Directed Mongrel with Physical Net Constraints |
| | Speaker(s): | Bill Halpin - Intel/Syracuse Univ., Santa Clara, CA
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| | Author(s): | Tung Cao - Intel Corp., Santa Clara , CA
Sung Hur - Syracuse Univ., Syracuse, NY
Amit Chowdhary - Intel Corp., Santa Clara, CA
Bill Halpin - Intel/Syracuse Univ., Santa Clara, CA
Yegna Parasuram - Intel Corp., Santa Clara , CA
Karthik Rajagopal - Intel Corp., Santa Clara, CA
Vladimir Tiourin - Intel Corp., Santa Clara, CA
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