Jan Rabaey - Univ. of California, Berkeley, CA
| | Organizers: Dennis Sylvester, David Blaauw
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| | Today's rising power densities are reminiscent of the end of the bipolar design era twenty years ago and are widely cited as the foremost challenge to continued CMOS scaling. On a more optimistic note, the power bottleneck provides excellent opportunities for EDA innovation in areas such as leakage reduction, power distribution, and low-power clocking. This panel brings together experts in circuit design and CAD tool development to discuss the current status of low-power EDA offerings and provide opinions on what new capabilities are most important in the power-constrained design era.
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| |  2.1 |
Reshaping EDA for Power
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| | Speaker(s): | Mark Horowitz - Stanford Univ., Stanford, CA
Andrew T. Yang - Apache Design Solutions, Inc., Mountain View, CA
Takayasu Sakurai - Univ. of Tokyo, Tokyo, Japan
Wolfgang Nebel - Oldenburg Univ., Oldenburg, Germany
Kerry Bernstein - IBM Corp., Essex Junction, VT
Jerry Frenkil - Sequence Design Inc., Acton, MA
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