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The purpose
of the DAC/ISSCC Student Design Contest is to promote excellence
in the design of electronic systems by providing competition
between graduate and undergraduate students at universities
and colleges.
40th DESIGN CONTEST WINNERS
OPERATIONAL CATEGORY
1st Place (Best Overall)
A Computationally Efficient ASIC Implementation
for the Decoding of Space-Time Block Codes
Enver Cavus, Babak Daneshrad - Univ. of California, Los Angeles,
CA
2nd Place
A Low-Energy Chip-Set for Wireless Intercom
(Session 52.2)
Josie Ammer, Michael Sheets, Tufan C. Karalar, Mika Kuulusa,
Jan Rabaey - Univ. of California, Berkeley, CA
3rd Place
Energy-Aware Design of a Real-Valued FFT
Alice Wang, Anantha Chandrakasan - Massachusetts Institute
of Tech., Cambridge, MA
CONCEPTUAL CATEGORY
1st Place
A 16-Bit Mixed-Signal Microsystem with Integrated
CMOS-MEMS Clock Reference (Session 31.1)
Robert M. Senger, Matthew Guthaus, Eric D. Marsman, Michael
S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Richard
B. Brown - Univ. of Michigan, Ann Arbor, MI
2nd Place
An Integrated Thermally-Based Microflow Sensor
Masoud Agah, Yang Li, Robert M. Senger, Kensall D. Wise -
Univ. of Michigan, Ann Arbor, MI
HONORABLE MENTIONS
Towards A Button-Sized 1024-Site Wireless
Cortical Microstimulating Array (Operational)
Maysam Ghovanloo, Khalil Najafi - Univ. of Michigan, Ann Arbor,
MI
Design Flow for HW/SW Acceleration Transparency
in the ThumbPod Secure Embedded System (Conceptual) (Session
5.1)
David Hwang, Patrick Schaumont, Yi Fan, Alireza Hodjat, Bo
Cheng Lai, Kazuo Sakiyama, Shenglin Yang, Ingrid Verbauwhede
- Univ. of California, Los Angeles, CA
Analog Turbo Decoder Implemented in SiGe BiCMOS
Technolgy
Wei Huang, Vinay Igure, Garrett Rose, Yan Zhang, Mircea Stan
- Univ. of Virginia, Charlottesville, VA
Design of a High Performance Security Coprocessor
Yunqing Chen, Jun Cheng, Tsung Hsing Hu, Jerry Kao - Univ.
of Michigan, Ann Arbor, MI
39th DESIGN CONTEST WINNERS
OPERATIONAL CATEGORY
1st Place $4,000
(session 41.1) Unlocking the Design Secrets
of a 2.29 Gb/s Rijndael Processor
Patrick R. Schaumont, Ingrid M. Verbauwhede, Henry Kuo - University
of California, Los Angeles, CA
2nd Place $2,500
System Design of iBadge for Smart Kindergarten
Ivo Locher, Sung I. Park, Andreas Savvides, Mani Srivastava
- Univ. of California, Los Angeles, CA
3rd Place (tie) $1,500
A Low Noise Switched-Capacitor Interface Electronics
for Sub-micro Gravity Resolution Micromachined Accelerometers
Haluk Kulah - Univ. of Michigan, Ann Arbor, MI
3rd Place (tie) $1,500
Low-Jitter Power-Aware Non-PLL Clock Generator
for GHz Microprocessors
Chulwoo Kim, Inchul Hwang - Univ. of Illinois, Urbana, IL
Sung Mo Kang - Univ. of California, Santa Cruz, CA
CONCEPTUAL CATEGORY
1st Place $4,000, SDC
Best Paper $1000
A Microsystem for Near-Patient Accelerated
Clotting Time Blood Tests
Steven M. Martin, Roy H. Olsson, Richard B. Brown - Univ.
of Michigan, Ann Arbor, MI
2nd Place $2,500
Design of a Crossbar Switch Chip for Use in
a Demonstration System of an Optoelectronic Multi-Chip Module
Jason D. Bakos, Donald M. Chiarulli - Univ. of Pittsburgh,
Pittsburgh, PA
3rd Place $1,500
Highly Parallel DNA Sequence Matching and
Alignment Processor
A. T. Patzer - Duke Univ., Durham, NC
HONORABLE MENTIONS $500
A Low-Power Line Driver Using Resonant Charging
With Reduced High-Order Frequency Components
Clemens Schlachta, Burkart Voss, Manfred Glesner - Darmstadt
Univ., Darmstadt, Germany
(session 29.4) Systematic Design of a 200
Ms/s 8-bit Interpolating/Averaging A/D Converter
Jan Vandenbussche - Katholieke Univ., Leuven, Belgium
Power Minimization for Digital Optical Interconnects
Xiaoqing Wang, Fouad Kiamilev, Jeremy Ekman - Univ. of Delaware,
Newark, DE
The contest will allow entries
of both integrated circuits and electronic systems (board-level
design). It will have two categories: 'Operational' and 'Conceptual'.
Operational
designs will have been implemented and tested. Proof of
implementation in the form of die- or board-photographs and
measurement data must be supplied.
Conceptual designs need not have been implemented but must have
been thoroughly simulated and must include a test plan.
CRITERIA FOR ENTERING THE CONTEST (SUBMISSION)
Submissions are invited from full-time
graduate and undergraduate students. The design must have
taken place as part of the students' course or research work
at the university and must have been completed within 18 months
prior to the submission deadline.
Submissions are made electronically
via the DAC web site. Student Design Contest papers should
include and abstract and should not exceed 6000 words, with
a recommended length of 4000. The deadline for submission
is December 20, 2002.
It is appropriate for a professor
to be included as a co-author if he/she was instrumental in
the student(s) approach to the design, or provided other guidance
that contributed to the success of the design.
Submissions are judged by a panel
of experts including members of the DAC Technical Program
Committee and other representatives from the industry. Judging
criteria includes originality, soundness of engineering, measured
performance and the quality of the written submission. Winners
will be notified in mid-February.
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