Speaker's Breakfast will be in Room 205AB on Tuesday, Wednesday and Thursday.
Pink background indicates Design Methods Sessions. Grey indicates Embedded Systems.
RM
BallroomAB
207A-D
210CD
210AB
209AB
Ses#
Session 36
Session 37
Session 38
Session 39
Session 40
8:30
to 10:00
Architectural Power Estimation and Optimization
Panel: Libraries: Lifejacket or Straitjacket?
Techniques for Reconfigurable Logic Applications
Test and Diagnosis for Complex Designs
Special Session: Highlights of ISSCC: High-Speed Heterogenous Design Techniques
BREAK 10:00 - 10:30
Ses#
Session 41
Session 42
Session 43
Session 44
Session 45
10:30 to 12:00
Special Session: Highlights of ISSCC and The Design of State- of- the- Art Microprocessors
Panel: Formal Verification: Prove it or Pitch it
High Frequency Interconnect Modeling
Novel Approaches in Test Cost Reduction
Retargetable Tools for Embedded Software
KEYNOTE -
The Tides of EDA
1:00 - 1:45 | Room: Ballroom A-C
Alberto L. Sangiovanni-Vincentelli
Professor, Univ. of California, Berkeley, CA
Ses#
Session 46
Session 47
Session 48
Session 49
Session 50
2:00
to
4:00
Special Session: ASIC Design in Nanometer Era - Dead or Alive?
Floorplanning and Placement
Advances in SAT
Novel Design Methodologies and Signal Integrity
Memory Optimization for Embedded Systems
BREAK 4:00 - 4:30
Ses#
Session 51
Session 52
Session 53
Session 54
Session 55
4:30
to
6:00
Special Session: Design Automation for Quantum Circuits
Energy-Aware System Design
Budgeting, Simulation and Statistical Timing
Interconnect Noise Avoidance Methodologies and Slew Rate Prediction
Analog Design Space Exploration
