Every low power design is different and tends to have its own interesting set of issues to solve. You have to think through various elements of chip design if you want to operate at very low power levels and you have to introduce appropriate design techniques early in the design cycle. This hands-on tutorial discusses predictive analysis techniques provided by Atrenta's SpyGlass LP product as means to help guide the construction of design description that is low power methodology aware. Typical low power design methodology now include gated clock domains for reducing design activity, voltage domains to reduce overall dynamic power, and power domains to reduce leakage power consumption. These techniques add complexity to the design process that must be taken into account early in the design cycle to create a power aware RTL.
SpyGlass LP provides a comprehensive set of RTL techniques addressing clock and voltage management needs of a design targeting low power goals. The use of multiple voltage domains introduces new issues in the design process. For example, signals that cross these voltage domain boundaries must be correctly level-shifted. Leakage power is a major concern with designs using the 90 nm process technology and more so for future process technologies. Shutting down portions of the design is the most effective way of dealing with leakage in the stand-by mode of operation. The design methodology involving multiple power domains in a design presents its own set of challenges. Being able to customize your project requirements is an important aspect of ensuring low power methodology goals. We will also briefly introduce the ability to customize your low power requirements using SpyGlass LP.
Every low power design is different and tends to have its own interesting set of issues to solve. You have to think through various elements of chip design if you want to operate at very low power levels and you have to introduce appropriate design techniques early in the design cycle. This hands-on tutorial discusses predictive analysis techniques provided by Atrenta's SpyGlass LP product as means to help guide the construction of design description that is low power methodology aware. Typical low power design methodology now include gated clock domains for reducing design activity, voltage domains to reduce overall dynamic power, and power domains to reduce leakage power consumption. These techniques add complexity to the design process that must be taken into account early in the design cycle to create a power aware RTL.