1 Panel: CEO PANEL: EDA: This is Serious Business
2 Special Session: HOT Leakage
3 Clock Routing and Buffering
4 Tools and Strategies for Dynamic Verification
5 Timing-Driven System Synthesis
6 Special Session: Reliable System-on-a-Chip Design in the Nanometer Era
7 Panel: When IC Yield Missed the Target, Who is at Fault?
8 Power Modeling and Optimization for Embedded Systems
9 Performance Evaluation and Run Time Support
10 Advances in Analog Circuit and Layout Synthesis
11 Power Grid Design and Analysis Techniques
12 Panel: What Happened to ASIC? Go (Recon)figure?
13 Methods for a Priori Feasible Layout Generation
14 Abstraction Techniques for Functional Verification
15 Memory and Network Optimization in Embedded Designs
16 Special Session: The Future of Timing Closure
17 Panel: Verification, What Works and What Doesn't
18 Design Space Exploration and Scheduling for Embedded Software
19 Advances in Accelerated Simulation
20 Design for Manufacturability
21 Statistical Timing Analysis
22 Panel: System-Level Design: Six Success Stories in Search of an Industry
23 New Ideas in Placement
24 Model Order Reduction and Variational Techniques for Parasitic Analysis
25 Compilation Techniques for Embedded Applications
26 Special Session: Platform-Based System Design
27 Innovations in Logic Synthesis
28 Yield Estimation and Optimization
29 High-Level Techniques for Signal Processing
30 Advanced Test Solutions
31 Advances in Boolean Analysis Techniques
32 Panel: Were the Good Old Days all that Good? EDA Then and Now
33 Power Optimization for Real-Time and Media-Rich Embedded Systems
34 Latency Tolerance and Asynchronous Design
35 New Technologies in System Design
36 Special Session: BioMEMS
37 Panel: Will Moore's Law Rule in the Land of Analog?
38 Floorplanning
39 Issues in Timing Analysis
40 Special Session: ISSCC Highlights
41 Special Session: Multiprocessor SoC MPSoC Solutions/Nightmare
42 Panel: Is Statistical Timing Statistically Significant?
43 Timing Issues in Placement
44 Design Methodologies for ASIPs
45 FPGA-Based Systems
46 Special Session: Security as a New Dimension in Embedded System Design
47 Leakage Power Optimization
48 Interconnect Extraction
49 New Frontiers in Logic Synthesis
50 Numerical Techniques for Simulation
51 Energy and Thermal-Aware Design
52 Noise-Tolerant Design and Analysis Techniques
53 New Tools and Methods for Future Embedded SoC
54 New Scan-Based Test Techniques
55 CAD for Reconfigurable Computing
100 Business Day: Competitive Strategies for the Electronics Industry
150 Business Day: Business Models in IP, Software Licensing, and Services
Pavilion Panel - EDA Consortium Panel: Does EDA Need an OS Roadmap?
Pavilion Panel - EDA Consortium Panel: Export Controls in the Age of Globalization

Copyright � 2003 by the Association for Computing Machinery, Inc. (ACM). Permission to make digital or hard copies of portions of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyright for components of this work owned by others that ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permission to republish from: Publications Dept. ACM, Inc. Fax: +1(212) 869-0481 or permissions@acm.org. For other copying of articles that carry a code at the bottom of the first or last page, copying is permitted provided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923.