Date Modified:     04/29/2004
Company Name:     ReShape
Booth Number:    4443,

Booth Number(s):  4443

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ReShape features products in the following categories:

• IC/ASIC Design Tools
Low-Power Design
Systems on a Chip

80 Word Final Program Company Abstract

Have a hierarchical headache? Are you struggling to meet QOR and schedule goals using hierarchical physical design? ReShape's advanced chip-level design tool suite automates the proven but labor-intensive hierarchical physical design methodology. ReShape delivers automated cross-block optimizations and full-chip production-GDSII iterations in less than 24 hours. Use ReShape to turbo charge your existing Cadence, Mentor, and Synopsys tool investment and realize the benefits of hierarchy with Virtual Flat quality. Step up to Chip-Level Design Automation!

Company Description

Leading edge design teams have dealt with growing System on a Chip, SoC, complexity and performance demands by breaking their SoC into multiple place and route block regions, a technique known as hierarchical physical design. ReShape is developing a new class of electronic design automation (EDA) software that automates away the challenges associated with hierarchical physical design. With ReShape tools you will focus on your full-chip design problems, and not be consumed with block-level construction details.
We are focused on delivering two important benefits:

Better silicon. We have patented full-chip optimization technology that realizes Virtual Flat (TM) results. Quality metric improvements include: 15% smaller die size (benchmark average) and 30% average reduction in inter-block interconnect wire and repeaters.

On time schedules. Projects slip because 1) full-chip issues are discovered late in the design cycle when all the blocks on the SoC are integrated as a full-chip, and 2) SoC design specifications change in the late stage. ReShape's patented build automation technology enables you to "compile" your netlist into full-chip GDSII in 24 hours or less using your existing Cadence and Synopsys tools. Fast implementation turns enable you to verify your design decisions using your "golden" verification tools overnight. Now you can know exactly where your design is in context of full-chip, all the time.