Management Day @ DAC Where Design Technology and Business Converge
Tuesday, June 14, 2005 • 8:00 am - 5:00 pm

As a manager in today's ultra-competitive electronics industry, you have major decisions to make every day. Do you choose best-of-breed tools or a single-vendor solution? Is an ASIC or foundry model right for your design? Which process node and IP should you use? How should you measure improved yield, cost, and time-to-volume ROI? And, which vendors can strengthen your supply chain?

To learn how managers from Philips, Intel, Freescale, Cisco, PMC-Sierra, and other leading companies make these and other design-business decisions, plan to attend Management Day @ DAC. The event will begin with a panel of supplier CEOs talking about how each is aligning his company's core competencies to support your design-business success.

Following the morning sessions, you'll attend the EDA Business Forum luncheon. The Forum will feature EE Times vice-president Richard Wallace presenting highlights of the new EE Times Reader Study, followed by keynote speaker Jon Kang, senior vice-president of the Technical Marketing Group at Samsung Semiconductor. Jon will talk about the future of the consumer electronics market. The Forum is sponsored by Ater-Wynne, CMP Media Electronics Group, The Design Automation Conference, D.A. Davidson & Co., the Market Statistics Service of the EDA Consortium, and Lanza techVentures.

At the end of the day, enjoy a Cocktail Party where you can network with the day's speakers and industry peers.

Participation in the Management Day @ DAC is a tremendous value at just $75. Click here to register now.

Management Day Schedule:

8:30-10:15 • KEYNOTE:
Bernard Myerson - IBM Fellow, Vice President and Chief Technologist, Systems and Technology Group, IBM Corp.
Ballroom ABC
How Does One Define "Technology" Now That Classical Scaling Is Dead (and Has Been for Years)?

10:30-12:00 • PANEL:
Differentiate and Deliver: Leveraging Your Design and Manufacturing Partners from Product Concept to Production
Room 207ABC
Chair: Jay Vleeschhouwer - Merrill Lynch, New York, NY
Panelists:
Warren East - CEO, ARM Ltd., Cambridge, UK
Michael J. Fister - CEO, Cadence Design Systems, Inc., San Jose, CA
Walden C. Rhines - CEO, Mentor Graphics Corp., Wilsonville, OR
Aart De Geus - CEO, Synopsys, Inc., Mountain View, CA
Jackson Hu - CEO, UMC Corp., Hsinchu, Taiwan

12:00-1:30 EDA Business Forum Luncheon sponsored by Ater-Wynne, CMP Media Electronics Group, The Design Automation Conference, D.A. Davidson & Ballroom E Co., the EDA Consortium, and Lanza techVentures

2:00-4:00 • SESSION 100: Choosing Flows and Methodologies for SoC Design • Room 207D
Chair: Dennis C. Wassung, Jr. - Adams Harkness, Inc., Boston, MA

100.1 EDA Flows: Best-of-Breed or Single-Vendor Solution?
Speaker(s): Magdy Abadir - Freescale Semiconductor, Inc., Austin, TX

100.2 The Criteria to Select: ASIC vs. Foundry Model
Speaker(s): Mark Bapst - Freescale Semiconductor, Inc., Rolling Meadows, IL

100.3 How to Choose from all the Process Nodes, IP Cores, and Other SoC Suppliers
Speaker(s): Norbert Diesing - PMC-Sierra, Inc, Burnaby, BC

4:30-6:00 • SESSION 150: How to Determine the Necessity for Emerging Solutions • Room 207D
Chair: Nic Mokhoff - EE Times, Manhasset, NY

150.1 Yield is all that Matters: How do you Judge Return on Investment?
Speaker(s): Kamalesh N. Ruparel - Cisco Systems, Inc., San Jose, CA

150.2 How to Meet Time-to-Volume Requirements
Speaker(s): Hao Nham - eSilicon Corp., Bedminister, NJ

150.3 Low-Power Design Decisions: How to Choose the Necessary Ingredients
Speaker(s): Francesco Pessolano - Philips Semiconductors, Eindhoven, Netherlands

150.4 Soft Errors: Do You Need to Worry, and When? Which Applications are Affected?
Speaker(s): Kee Sup Kim - Intel Corp., Sacramento, CA

6:00-6:30 • Wrap-up Cocktail Party Room 207D.