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 MONDAY | TUESDAY | WEDNESDAY | THURSDAY | FRIDAY  |
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| Speaker's Breakfast is in Room 205AB at 7:30 am Tuesday, Wednesday and Thursday. | |
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THURSDAY
Exhibit Hours - 9:00 am to 1:00 pm |
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| Ses# | Session 36 | Session 37 | Session 38 | Session 39 | Session 40 | HoT | |
| 8:30 to 10:00 | SPECIAL
SESSION: Matlab(TM) - The Other Emerging System-Design Language |
PANEL: Should Our Power Approach Be Current? |
Emerging Ideas in Energy Management Techniques |
Advances
in Optimization of Mixed-Signal Circuits |
Circuit Performance Under Parameter Variation |
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| BREAK 10:00 - 10:30 am | |||||||
| Ses# | Session 41 | Session 42 | Session 43 | Session 44 | Session 45 | ||
| 10:30 to 12:00 | SPECIAL SESSION: Formally Verifying Your 10-Million Gate Design |
Embedded Hardware and System Software |
Power Estimation and Design Tradeoffs |
Programmable Architectures |
SAT: Cool Algorithms and Hot Applications |
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| KEYNOTE
- Innovation
in the EDA Business Need Not Be an Oxymoron 12:45 - 1:45 | Ballroom ABC Ronald A. Rohrer - Cadence Design Systems, Inc., Santa Clara, CA | |||||||
| Ses# | Session 46 | Session 47 | Session 48 | Session 49 | Session 50 | HoT | |
| 2:00 to 4:00 | SPECIAL SESSION: DFM and Variability: Theory and Practice |
Tools
and Methods for the Verification of Processors and Processor-Based Systems |
Electrical Optimization for Physical Synthesis |
Optimization Techniques in High-Level Synthesis |
Testing
for Process- and Timing-Related Faults |
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| BREAK 4:00 - 4:30 pm | |||||||
| Ses# | Session 51 | Session 52 | Session 53 | Session 54 | Session 55 | ||
| 4:30 to 6:00 | SPECIAL SESSION: Hierarchical Design and Design Space Exploration of Analog ICs |
PANEL:
Platform ASIC Apprentices: Who Will Survive Your Boardroom? |
Dynamic Voltage Scaling |
New Directions in FPGA Technologies |
Reduced Order Modeling |
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