43rd
Design Automation Conference, July 24-28, 2006
July 20, 2006




Verification hot box - up to 200 screaming MHz - the fastest verification and most cycles per dollar. Learn why so many ESNUG users are raving and why 8 out of the top 10 semiconductor companies use EVE. Run full chip testbenches at MHz speed, verifying HW&SW together, before tapeout. EVE gives you both emulation and ASIC prototyping in one affordable platform.

Eleventh Workshop on Women in Design Automation: Ellen Yoffa to receive the EDA Achievement Award

Gabe Moretti, editor

The Workshop for Women in Design Automation is a highlight of DAC. This unique program, started in 1995, has continued to grow each year and affords the opportunity to hear successful women speak on topics relevant to their careers. It also gives participants the opportunity to network with their peers and engage in an exchange of views and ideas that foster growth. This year's event will be held Monday, July 24, from10:00 am -12:45 pm. Workshop registration ($50 for IEEE or ACM members and $75.00 for non-members) includes access to the exhibition and demo suites on Monday as well as Continental breakfast and registration 9:00-10:00am, and lunch 12:45-1:45pm.

The theme of the workshop is: Working the 80/20 Rule for Success -- Focusing in on What Matters. Daya Nadamuni, Research VP at Gartner Dataquest and Chair of the event, said: "The workshop's accomplished keynote speaker and panelists will provide insights into how to work the 80/20 rule for success, showcasing their own real-life examples and providing practical suggestions." Workshop attendees will learn how these talented women "cracked the code" and learned how to focus on the 20% that mattered and enabled them to achieve the 80% results for career success and work/life balance. Obviously most men could benefit from these insights as well and they are welcome to register.

Marie R. Pistilli Women in EDA Achievement Award is a major cornerstone of the Workshop. Women have made important contributions and strides in the EDA industry for over 20 years. In an effort to recognize those who have dedicated time towards these achievements, the DAC Executive Committee presents an annual award to honor an individual who has made significant contributions in helping women advance in the field of EDA technology. This year, the award will be presented to Ellen Yoffa of IBM who is a former DAC chair.

Reynette Au, Vice President Business Licensing, nVIDIA Corporation, will deliver the keynote address. With more than 20 years of management experience in the semiconductor industry, she is responsible for building the company's IP licensing business and positioning it as a complementary and strategic partnership-building model across all nVIDIA businesses.

A panel discussion will follow the keynote speech. It will provide an opportunity to learn how prominent professionals in the industry have made career choices to achieve a rewarding personal and professional life experience. Each of us has the chance to influence our organization in fundamental ways if we have the tools. Building on the work described in the keynote, the panelists will describe their own experience about the impact they have made on their organizations. Sabina Burns of Virage Logic, Vice Chair of this year's workshop will moderate the panel. The panelist are: Denise Brouillette, The Innovative Edge, Eileen Sullivan, Cadence Design Systems, Inc, Kathy Papermaster, IBM Corp., Soha Hassoun, Tufts University, and Sophie Maxell, San Francisco City Supervisor.
To register and for more information on the workshop and DAC Conference visit http://www.dac.com/43rd/index.html

CEDA will feature a talk on embedded deterministic test at DAC

Gabe Moretti, Editor

In order to coordinate various EDA activities within its fold, the IEEE last year created the Council on Electronic Design Automation (CEDA). In addition to the coordinating function CEDA intends to enable new initiatives, foster interdisciplinary research and recruit young talent to EDA. The new organization has taken over the sponsorship of two important conferences, DAC and ICCAD from various IEEE Societies. CEDA will present one of its Distinguished Speaker Series events during this year's DAC. Monday, July 24 in Room 124 of the Moscone Center from 5:30 to 7:00 PM attendees will be able to hear Dr. Janusz Rajski talking about embedded deterministic test. Dr. Rajski, chief scientist and director of engineering for Design-for-Test at Mentor Graphics, is the winner of this year's IEEE Transaction on CAD Best Paper Award.

"We are planning a lively and interactive discussion during DAC to give the audience an opportunity to learn more about embedded test," says Andreas Kuehlmann, CEDA's vice-president of technical Activities. "The Distinguished Speaker Series is meant to be educational and tutorial and not at all intimidating. We welcome all DAC attendees to join us for an enjoyable evening of learning and networking".

The event is open to all and offers a beer and refreshments reception before the talk to provide attendees with the means to network and to learn more about CEDA.

Gabe Moretti, Editor



Let us know what you think: news@dac.com.

You can see the complete advanced program of the 43rd DAC on the web by navigating the Conference Program tab, choosing Technical Sessions and then clicking on the type of session you are interested in.

View the Exhibitors Find the newest technologies from over 240 companies on the show floor.

View the 42nd DAC Proceedings

DAC Newsletter - Verification (Can you hear me now?)

by Clive (Max) Maxfield

The last house I owned when I lived in the UK was built in 1789, which was the year of the French revolution. This was just before I moved to Huntsville, Alabama, USA in 1990 for the nightlife (that's a little Alabama joke). The reason I mention this little nugget of trivia is that the editorial deadline for this newsletter is July 14th, which is the French national holiday, known in France as "Fete National" (National Holiday) or simply "14 Juillet" (July 14th).

Of course, this holiday is known as "Bastille Day" in English. In fact, even in France, it is commonly associated with the storming of the Bastille, which took place on 14th July 1789. As it happens, however, the Fete National actually commemorates a huge feast called the "Fete de la Federation," which was held a year later on the 14th July 1790 to celebrate what the folks at the time considered to be the end of the French revolution.

And why do I bother bringing all of this up here? Well, like many folks, I've long assumed that, on the basis we call the 14 th July "Bastille Day," this holiday was intended to celebrate the storming of the Bastille, but before putting pen to paper (or fingers to keyboard), I thought I'd better check things and VERIFY my facts.

"Good grief," I hear you cry; "That was one smooth segue into the topic of verification!" And you'd be right, because it was! So, just what is verification? Well, one of the more appropriate dictionary definitions would be: "An additional proof that something that was believed (some fact or hypothesis or theory) is correct." In the context of electronic designs, some amongst us might further generalize this to refer to some way of demonstrating that our design will perform its desired function without errors.

But wait, because the purists will say that there's more to the life of an electronic component or system than "function," there's also performance, power consumption, shape, size, weight, color, smell (well, maybe not smell, but you get my drift). The bottom line is that any design that doesn't conform to all of the requirements in the original specification is probably not going to be successful in its target market. In turn, this means that all aspects of the design have to be verified by one means or another.

You may have started to think that I'm being a little vague here. You would be right. The problem is that the word "verification" means different things to different people. In the case of a RTL logic designer, for example, verification might refer to simulation. By comparison, someone in charge of the physical portion of the design (floorplan-place-route) may have a completely different point of view. And when we move into the manufacturing domain, they have their own take on things.

In reality, there are a humongous number of companies involved in verification in one form or another; far too many to mention all of them here. So what I'm going to do is to introduce a series of "buckets" (verification categories) and perhaps be tempted to mention a few example companies that fall into each group.

The Emerging Top End

Let's commence with what we might call the emerging top end. In this case, I'm thinking of companies like VaST, Virtutech, and Virtio who develop high-level system models called Virtual Prototypes (VPs), Virtual System Prototypes (VSPs), or Virtual Platforms (VPs again). These are functionally accurate (sometimes timing-accurate) software model of the entire system that can simulate the behavior of the system at anywhere between 50 to 200 MIPS.

There are several reasons we might think of these tools in the context of verification. For example, it's possible for system architects to run real software loads on these platforms to verify that the system will meet its bandwidth, performance, and power consumption goals. Also, software developers can use them to verify that their firmware and embedded applications will run without errors in advance of having any actual hardware to play with.

Actually, there are a wide variety of companies/tools that fall into this "emerging top end" category. For example, there's the rather cunning sequential analysis technology from Calypto that allows you to verify that two representations of your design with different temporal behavior (say a different number of pipeline stages) are functionally equivalent (that is, to ensure you will eventually get the same answers out of both implementations).

Then there are companies like Chipvision or PowerEscape, whose very high level of abstraction power estimation technology allows you to verify that your design will meet its power consumption specifications. And there are also companies one might not traditionally think of in this arena, such as Poseidon. Most amongst us would cast Poseidon in the role of synthesizing C code into hardware accelerators, but in fact this also involves a lot of verification to ensure that the ensuing hardware/software mix will meet its power/performance/whatever goals.

The Solid Center

This category refers to tools and techniques such as simulation, emulation, formal verification, assertion-based verification (ABV), and such like in the context of languages like VHDL, Verilog, SystemVerilog, and SystemC.

This is where the "big boys" like Cadence, Mentor, and Synopsys tend to play the hardest, and all of these companies have incredibly sophisticated offerings. The Incisive Enterprise Verification Platform from Cadence makes my head spin, for example, while Mentor and Synopsys also have their own mega-powerful tools and methodologies.

But there are a lot of other interesting companies in this "as, for example, have made themselves a very nice niche with regards to analyzing and verifying results for predominantly digital designs. Meanwhile, Sandworks are busily forming their own corresponding niche in the analog and mixed-signal domain.

And the list goes on, with companies like EEsof in the analog/RF domain, OneSpin with their rather cool formal verification solutions, and Knowlent with their high-speed serial interface verification IP (VIP). Then there are the folks at Tenison with their RTL-to-C technology and Carbon with their ability to convert RTL representations into extremely high-performance simulation models.

It would also be remiss of us to neglect companies like Gradient with their full-chip-level thermal analysis and verification solutions; also Flomerics with their package-level equivalent (Gradient and Flometrics recently announced that they are collaborating on an all-singing-all-dancing full-chip-package solution).

Last but not least, we mustn't forget Jasper who ... well, actually, I don't know what they do, but my friend Brian Bailey who is an expert on verification mentioned that they had some cool technology, and that's certainly good enough for me (I'll wander round to their booth at DAC and ask them some probing questions).

The Forgotten Realm

This bucket refers to all of the gate-level and back-end verification such as linting tools for the RTL code and equivalence-checking and such like. The problem here is that, although we can all agree that these tools are incredibly useful and totally necessary, it's real easy to forget about them ... in fact, off the top of my head, I can't think of a single company that plays in this arena (which sort of proves my point).

Into the Bowels (of Manufacturing)

Truth to tell, I hadn't really thought about this until recently ... as a design engineer (by trade), manufacturing has always been a "far off country" to me; and than I ran into a company called Brion. Here's the deal; when we develop a silicon chip, the output from the logical and physical design portion of the flow is the suite of GDSII files that the manufacturing team at the foundry will use to create the photomasks that will - in turn - be used to generate the chips.

The problem is that the structures we are creating on the surface of today's chips are smaller than the wavelength of light we're using to create them. This means that if the photomasks are created using the GDSII as-is, the result will be something that won't "print" correctly.

In order to address this, the GDSII files are post-processed with a variety of resolution enhancement techniques (RET); for example, optical proximity correction (OPC), which modifies existing features or adding new features - known as sub-resolution assist features (SRAF) - so as to obtain better printability.

But as the great Roman satirist Juvenal said (sometime around the latter part of the 1st century or the early part of the 2nd second century; possible on a Thursday morning around 9:00 am, but probably not) -"Quis custodiet custodes? " which translates as"Who will guard the guardians themselves?" The fact that this quote arose in a discussion concerning the usefulness of eunuchs guarding one's womenfolk isn't important here (I bet you thought it was someone talking about the Emperor's guard, didn't you?). My point (yes, there is one) is that once you've run your OPC application, how do you know that it performed its job correctly?

And so - finally - we come to Brion, who have a rather cunning OPC verification solution (trust me, they would be absolutely delighted if you were to wander up to their booth at DAC and ask them about it - just mention my name - it won't do you any good, but it will make me feel happy, so that's OK). Actually, Brion's technology is really rather clever, but ... sad to say, we're wandering off track into the weeds (I know, it's hard to believe I would do that, but there we are).

The point is that verification (which, you may recall, is the topic of this newsletter - stick with me - you have to stay focused here) pops up in a tremendous variety of different guises throughout the design and manufacturing flow. As designs become larger, more complex, and more demanding, existing verification solutions are evolving to meet the challenge and new solutions are appearing like rabbits out of magicians' hats.

As always, I can't wait to see what new verification tools, technologies, and methodologies will be on display for our delectation and delight at this year's DAC. I look forward to seeing you there. Feel free to come up and say "Hi" (especially if you have a beer you wish to share). Until next time, have a good one!

Further Reading

If you want to know more about verification in general, then there's always "Comprehensive Functional Verification: The Complete Industry Cycle" by Bruce Wile, ISBN-10: 0-12-751803-7 (or ISBN-13: 978-0-12-751803-9). This is a 700 page behemoth, but it's certainly one of the more comprehensive books on the topic.

And, of course, there's "The Functional Verification of Electronic Systems" by Brian Bailey, ISBN: 1931695318. This little rascal provides a comprehensive overview of functional verification, including coverage, simulation, testbench automation, transaction-level modeling, and assertion-based verification.

Then there's the recently published "EDA for IC System Design, Verification, and Testing" edited by Grant Martin and friends, ISBN 0849379237. Part of a two-volume set, this little scamp ranges far and wide across the verification landscape.

And last but not least, there are a bevy of new books on other topics rolling off the printing presses with this year's DAC in mind. These include:

"Networks on Chips: Technology and Tools" by Giovanni De Micheli and Luca Benini, ISBN 0-12-370521-5, which is claimed to be "A must on the bookshelf of anybody having an interest in SoC design."

"Customizable Embedded Processors: Design Technologies and Applications" by Paolo Ienne and Rainer Leupers, ISBN 0-12-369526-0, which is modestly predicted to "serve as the standard reference on this topic."

"Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores" by Steve Leibson, 0-12-372498-8, which has a quote by yours truly on the back cover, so you know its going to be a humdinger.

"VLSI Test Principles and Architectures: Design for Testability" edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, ISBN 0-12-370597, which is said to be "a 'must read' for anyone focused on learning modern test issues, test research, and test practices.

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Clive (Max) Maxfield is author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and The Design Warrior's Guide to FPGAs (Devices, Tools, and Flows). Max is also the co-author of How Computers Do Math</i>, featuring the pedagogical and phantasmagoric virtual <i>DIY Calculator (www.diycalculator.com).

In addition to being a hero, trendsetter, and leader of fashion, Max is widely regarded as being an expert in all aspects of computing and electronics (at least by his mother). Max was once referred to as "an industry notable" and a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.

Copyright © 43rd Design Automation Conference
5405 Spine Rd. Suite 102 - Boulder, CO 80301 USA

A note from the DAC Committee:

For all of you practicing "Just in Time" management, Registration for the 43 rd DAC is still open on the web and you will also be able to register at the conference. So, lack of planning is no excuse to experience the unparallel blend of San Francisco food and atmosphere with the leading technology EDA has to offer. Throw in fascinating keynote speeches, good after hours parties, a terrific technical program bound to each something new to each of us, and the chance to network and organize company reunions with the alumni from your previous companies, and you have all the ingredient for a career improvement opportunity.

So, either go to www.dac.com or bring your plastic money to the Moscone center. It is a move you will not regret.

Apache's market leading "power and noise integrity" solutions deliver dynamic power analysis, low power and leakage management, and SoC noise control for ultra-deep-submicron designs at 65nm and below. Apache's low power solution includes full-chip ramp-up simulation, MTCMOS switch optimization, and impact on timing analysis of mixed-mode operations. For more information, visit www.apache-da.com.

Jasper Design Automation's JasperGold Verification System is the first verification product to deliver systematic complete verification. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development.
JasperGold automatically isolates bugs with a unique static debugging capability. Visit http://www.jasper-da.com.

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OneSpin's 360 Module Verifier assures error-free operation of digital modules and IP by formally verifying their RTL design against a provably complete and correct set of transaction view properties. The tool identifies any gaps in the property set and automatically proves that the final property set is complete, achieving the true functional sign off that coverage driven methods cannot deliver.