Carbon Design Systems, a leader in virtual system prototyping solutions, will have an exhibit booth theater at DAC06. The theater program will include presentations from ARM®, CAST, Novas, SpiraTech, and Carbon and will cover advances in ESL design methodology including: architectural profiling, transaction-level modeling and debug, RTL import to ESL environments, and IP for low-power design. Booth #606 More info:

Tools to develop MEGA products and more

Today's complex SoCs require an integrated development flow because their operational characteristics and their manufacturability depend in part on design tradeoffs made at the very beginning of the development process. Therefore in surveying the exhibitors and deciding how to introduce a few of them to you we had to group a number of market segments in one overview article. The article is not meant to be a complete list of all of the exhibitors, that would be too long, but to provide you with an overall idea of the type of products you will see demonstrated at the 43 rd DAC. I could not think of a better person to tackle such a complex article than Max Maxfield. His volcanic brain, the easy colloquial writing style, and the global understating of EDA applications have not let me down. His article takes you through a development flow of a digital design from specification to GDSII and beyond. Future articles will present analog issues as well as cover the design verification market. See you on the exhibit floor in July.

Gabe Moretti, Editor


Let us know what you think:

You can see the complete advanced program of the 43rd DAC on the web at and then pull down on the Conference Program tab, choosing Technical Sessions and then clicking on the type of session you are interested in.

View the 42nd DAC Proceedings

View the Exhibitors

ESL, Power, Interconnect, and DFM (Oh My!)

It was a dark and stormy night ... I was happily ensconced in my command seat in the heart of the "Pleasure Dome" (my office), when an email from Gabe Moretti (of fame) trickled its way through the Internet and - with a fanfare of trumpets - appeared on my desktop.

How exciting! Gabe informed me that he had been appointed editor of the DAC 2006 newsletters, and asked if I would care to join the team and write two of them. "Cool Beans," said I, so what's my first topic. "ESL, Power, Interconnect, and DFM" replied Gabe.

What? Give me strength! How are we going to bring these diverse topics all together into one coherent newsletter? Well, I suppose we shall see as we proceed (as I pen these words, I'm looking at a totally blank document below this point, wondering what I'm going to say next).

... I'm still waiting ...

... OK, here it goes ...

Electronic System Level (ESL)
Last year I posed the question - "What the Hell is ESL?" - and I'm still as confused as I ever was. It is reassuring to note that I am not alone! To some folks ESL means designing at a high level of abstraction prior to making any hardware/software portioning decisions; to others is means hardware/software co-design; while still others would say that ESL refers to anything that's at a higher level of abstraction than register transfer level (RTL) representations. And of course, the Holy Grail of ESL is the executable specification. May be I will pitch the concept to a Hollywood type. And, of course, ESL can apply to both design and verification applications (this topic is for a later newsletter). The Mathworks, with both its products MATLAB and Simulink, has pioneered the field of executable specification and made "Model Based Design" its corporate motto. Many traditional EDA vendors have built links to these two products and a significant number of communication systems developers have used either or both products during the initial phase of design.

Returning to ESL design tools, a classic example is Catapult C from Mentor that allows you to take un-timed C/C++ representations and translate them into RTL. Alternatively, coming at things from a completely different direction, we have Bluespec who have augmented SystemVerilog and SystemC to provide some very interesting capabilities. And, of course, we have all of the usual suspects, such as CoWare with their sophisticated suite of platform-driven ESL design tools, and Forte with their SystemC synthesis suite and their new transaction level model (TLM) synthesis capabilities.

One very interesting area to me is that of creating virtual system prototypes, of which there are many flavors. Some of the companies that play in this arena are VaST, Virtutech, and Carbon.

There are also a number of companies who take C/C++ algorithms and programs, analyze them, and then generate hardware accelerators and/or coprocessors; for example, Poseidon. In a somewhat related approach, we have companies that take binaries (executables) and do much the same thing; for example, Binachip, and CriticalBlue. And then we have the folks who allow you to analyze your C/C++ programs and generate full-blown processor cores. Perhaps the best known of these is Tensilica, but there are also some perhaps less-familiar players such as Target.

Feel the Power!One of the big problems faced by designers of today's silicon chips is the amount of power they burn. Thus, a number of EDA companies are focusing on this issue. But how can we make a nice segue from the previous ESL topic into power? Well, how about ChipVision Design System who has been around for a few years and whose Orinoco allows designers to optimize their ESL design for low power consumption.

Or, how about Sequence Design, who focus on low-power design, with capabilities ranging from early RTL analysis to full-chip power estimates for today's largest designs. And how does this relate to ESL? Well, both CoWare and Forte's ESL environments can employ Sequence's power-analysis capabilities to generate power data that can be used for simulation and system analysis to optimize system architectures for power and performance (try saying that ten times quickly!).

Was that smooth or what? And then there are companies like ArchPro, whose multi-voltage RTL simulator lets users simulate the effects of any voltage variation at the register transfer (RT) level so as to facilitate the verification of multi-voltage functionality, connectivity, and sequencing. And, of course, there are the names we all know, such as Apache Design Solutions, who are justifiably famous for their full-chip transient, waveform accurate, power analysis and optimization solutions.

But wait, there's more, because we also have companies like Zenasis. Following conventional RTL and/or physically-aware synthesis, these little tricksters have tools that can analyze the design and then individually tweak the transistors forming the cells in a standard cell ASIC library to boost the performance of the gates in the critical paths while reducing power consumption in the gates forming the non-critical paths (in the case of a fab-less design house, Zenasis also has tools that use existing cells to form new cells).

Are You Well Connected?

I bet you're all aquiver with anticipation to see how we transition from power to interconnect. Well watch this (like a magician, the quickness of the hand deceives the eye).

Here's the deal, today's multi-million SoCs typically comprise large numbers of processor cores, DSP cores, hardware accelerator blocks, peripheral blocks, and memory subsystems. Currently, the prevalent technique for tying all of these subsystems together is to use multi-level synchronous bus and cross-bar structures, but keeping everything synchronized is a real pain.

In order to address this, several EDA companies are focusing on different techniques for implementing network-on-chip (NoC) architectures (actually, many of these tools could be considered to have ESL-type qualities and attributes). Companies like Arteris and Sonics immediately spring to mind. Also of interest in this arena is PolyCore Software that focuses on providing a virtual communications layer that abstracts application software from the underlying network.

But we digress... In addition to the problems inherent in keeping everything synchronized, many interconnect architectures are constantly burning power, because even when they aren't doing anything they are still being clocked. The solution according to one NoC company - Silistix - is to move to a fully self-timed (asynchronous) NoC. In this case the data - which is sent in packets - flows as fast as possible between stages because there is no waiting for clock edges and their traffic loads dictate the power consumed by the busses (there, I knew we could tie everything together).

But Can We Build the Little Scamps?

OK, we're doing pretty good so far, but can we possibly attach design for manufacturing (DFM) to our previous interconnect topic so as to put the final link in the chain? You betcha!

In the context of silicon chips, DFM refers to a variety of techniques used during the process of creating the design so as to facilitate its being manufactured. Also, the term "yield" refers to the number of die that work as a percentage of the total number of die on a silicon wafer. Hence, design for yield (DFY) refers to any techniques used to improve the yield of a particular device. As far as I'm concerned, these concepts and techniques are so intertwined that I've started to consider them as being a single "DFM/DFY" entity. The above-mentioned Gabe Moretti continues to say that this union should be called DFP (Design for Profit).

Actually, as with so many things in electronics and EDA, DFM means different things to different people. For many folks, DFM refers to post-processing the GDSII files used to create the photo-masks with a variety of resolution enhancement techniques (RET), such as optical proximity correction (OPC) and phase shift mask (PSM). However, a lot of people are starting to proclaim (in rather loud voices) that the 'D' in "DFM" stands for "Design", which means that we should drag DFM concepts upstream into the design flow. And so we come to companies like Pyxis Technology, focusing on developing new DFM-aware routing software for today's complex chip designs. (For "routing" read "interconnect", which neatly ties us back to the previous topic ... YES!)

Similarly, companies like Aprio Technologies are working furiously on upstream design tools that understand downstream lithographic/printing processes and effects, and that are capable of detecting and repairing performance and yield-robbing errors. Also, we have companies like Ponte Solutions who have been working on some cunning yield modeling, analysis, and optimization techniques. And there are some "new kids on the block" like Nanno SOLUTIONS, who are just now launching their company and announcing a range of DFM/DFY products.

But wait, there's more, because we also have companies like Blaze DFM who are promoting a concept they call "Electrical DFM." In a nutshell, this refers to a tool that drops in neatly between the design and manufacturing flows. Once you've generated your GDSII files, their tool analyses these files and provides "suggestions" to the downstream manufacturing engines to individually tweak all of the elements forming the design. For example, it may suggest varying the size of a transistor channel to make it slower (so long as it isn't on a critical path), thereby cutting down on the leakage power associated with that transistor.

And for those amongst us who don't think any of the existing tools "cut the mustard", we have companies like SoftJin Technologies who provide what they describe as: "A post-layout EDA application development toolkit that enables chip designers and photo-mask creators to develop their own cutting-edge yet customized post-layout tools - especially DFM/DFY tools - rather than force-fitting standard offerings.

And last but not least - just to increase our delectation and delight - there are companies like Clear Shape Technologies who are still running in stealth mode, but the word on the street is that they will be showing a new DFM offering at DAC.

Good Grief Charlie Brown!

Of course, it's important to remember that the companies mentioned above are simply offered as examples: there will doubtless be many more folks with exciting news in all of the areas discussed in this newsletter.

Well, I don't know about you, but - as always - I'm tremendously excited and enthused to see all of the evolutionary and revolutionary offerings that will be on show at this year's DAC. And so I bid you adieu. I look forward to seeing everyone at DAC. Please feel free to come up and say "Hi" (especially if you have a beer you wish to share). Until next time, have a good one!


Clive (Max) Maxfield is author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and The Design Warrior's Guide to FPGAs (Devices, Tools, and Flows) , Max is also the co-author of How Computers Do Math , featuring the pedagogical and phantasmagorical virtual DIY Calculator.

In addition to being a hero, trendsetter, and leader of fashion, Max is widely regarded as being an expert in all aspects of computing and electronics (at least by his mother). Max was once referred to as "an industry notable" and a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.

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Apache's market leading "power and noise integrity" solutions deliver dynamic power analysis, low power and leakage management, and SoC noise control for ultra-deep-submicron designs at 65nm and below. Apache's low power solution includes full-chip ramp-up simulation, MTCMOS switch optimization, and impact on timing analysis of mixed-mode operations. For more information, visit

Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence power and signal-integrity solutions give customers the competitive
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Blaze DFM provides solutions to designers at fabless semiconductor companies and IDMs seeking to reduce leakage power and minimize timing and power variability. Blaze's electrical DFM product, Blaze MO, provides dramatic improvements in leakage power and parametric yield. It is easy to add into any existing design flow and is supported by a broad range of foundries.

Free 4th Annual ESL Technology Symposium focused on "ESL at Work" for "IP selection, integration, and interoperability". Learn how ESL - through early expansive exploration and analysis of IP and architectures, and selection of the correct key partners - is solving the flow integration problem and providing a solution that meets market windows and improves
chances for first-pass silicon success.

Pyxis Technology is developing a new physical design system addressing
manufacturability and yield issues for sub-100nm technologies. A new
architecture has been developed to provide automated DFM routing. To bridge the gap between design and manufacturing, Pyxis is working with an ecosystem of DFM partners to implement feed-forward and feedback loops to ensure successful IC manufacturing for 65nm and below.