Design Automation Conference, July 24-28, 2006
June 23, 2006

The script for a reality show

When I asked Tets Maniwa to write an article about Analog Design tools, he mused that it would read like the plot for a TV Reality show: suspense and difficult obstacles to overcome are the stuff of today’s analog market segment. Thinking about it, analog is indeed the reality: the invention of the microprocessor created that artificial heaven we know as the digital domain. Things are simpler when you only deal with the artificial world of 1’s and 0’s. But as the famous commercial advised: “You can’t fool Mother Nature”. Well, at least not forever. And so, digital design now is confronted with a host of analog problems that, just a couple of technology nodes ago, languished in second order parameters limbo. As with all new market sectors, the dust has not completely settled in the analog domain: Tets provides you with a good introduction to the analog side of the 43rd DAC. Just remember: the steps you take on the exhibit floor are digital, but the length of the stride is analog.

Gabe Moretti, Editor

Let us know what you think: news@dac.com.

You can see the complete advanced program of the 43rd DAC on the web by navigating the Conference Program tab, choosing Technical Sessions and then clicking on the type of session you are interested in.

View the Exhibitors  Find the newest technologies from over 240 companies on the show floor.

View the 42nd DAC Proceedings

IC Design, the Non-Digital Tools

Some of this analog, mixed-signal, RF stuff is very hard to do.
by Tets Maniwa

Analog and mixed signal designs continue to challenge the design community. The Fabless Semiconductor Association forecasts that soon over 80 percent of all designs manufactured by their members will include analog and mixed signal components. This figure is probably closer to 100 percent if you include PLLs and I/O structures, as the latter classes of components are not digital but actually all highly optimized analog subsystems. All of the high-speed interfaces like gigabit Ethernet or Infinitiband use differential signals to avoid the problems of single-ended, discrete voltages for 1's and 0's.

The tools for digital design are evolving to accommodate the analog functions at a behavioral level, with functions described in C or AMS extensions to the HDLs. Some of the digital tools are changing to include the analysis of analog functions. Analog characteristics dominate timing, power, thermal, I-R drop and ground bounce, noise effects and signal integrity. These include non-linear responses, input and output signal characteristics, complex impedance loads, and interconnect behavior.

To address the increasing analog nature of the signals racing through an SoC, tools and models are changing. Because the parasitic effects of a design are no longer considered independent, the process, voltage, and temperature models of the devices and cells in a design must include analog-type units of measurements. The simple 0-1 and timing models have gotten so inaccurate that they are considered useless for process nodes below 130 nm. Now, the timing/power/noise/voltage models for a logic cell almost look like an early Ebers-Moll transistor, with Miller feedback capacitance, and complex input and output impedance characteristics.

Device and process variability borrows another analysis technology from the analog design side. Monte Carlo analysis changes the values of specified parameters within a range to determine sensitivity to parametric shifts and circuit response to combinations of parameters that don't fit on one of the "corner" cases. This process, coupled with fast Spice simulation, facilitates a more comprehensive analysis of a design without requiring hundreds of discrete models for the various voltage islands and other operating conditions.

Getting away from the digital side of design, the analog functions are also getting more complex. In older designs, the analog subsections only had to handle fairly low frequency signals and consisted of gain stages and transformation stages. The input stages had to change input signals from transducers to measurable voltage or current. Now, the analog stages must not only handle the transforms, but must also perform bandwidth and signal amplitude limiting, so the analog to digital converters and DSP sections have something reasonable to work with. Some of the analog systems have to handle bandwidths of hundreds of megahertz and upper frequencies over a gigahertz.

The challenges of designing, and the capabilities of the tools for those designs, are changing as the analog subsystem complexity increases. When the analog sections comprised a few hundred active devices and up to a thousand passive components, almost any Spice simulator could do the job. In fact, some of the analog designers who are creating small building blocks still use paper and pencil and calculators for much of their work. Another facet of this mode of design is that the circuit topology and the physical design are closely linked. The analog designers of yore were both helped and hindered by a need to have a comprehensive view of the design.

Now, however, it is not realistic to expect the small-scale tools to be adequate when the target is a multimedia processing block or a Bluetooth wireless link. Most analog subsystems are just that, subsystems. As signal processing moves more to the digital domain, the analog sections consume less and less of the total space on an IC. So the analog design tools have to become tightly coupled to the digital simulators at least by the time when the big regressions suites start running.

Even the designs that need a larger portion of analog than digital components have to work at least partially with a digital back-end set of implementation tools. So all of the design tools have to get orders of magnitude increases in speed and capacity to handle the analog portion and its interfaces to the digital sections. In addition to speed and capacity, the tools should increase the levels of automation available to the analog, mixed-signal designer. The need for very short total design times means that the analog designers no longer have the luxury of manually hand-crafting and fine-tuning a circuit, but must look to new design tools that can automate much of the refinement process.

So what can the designers that are doing analog, mixed-signal, power, and RF work expect to see at this year's DAC? There is a track called "Analog and Circuit" that looks at the issues associated with the non-digital design, analysis, and implementation issues. Sessions 3, 15, 51, and 57 are specifically focused on the types of design environments that boggle the minds of the digital crowds, the design and analysis of Spice-level circuits.

One panel, number 40, "Tomorrow's Analog: Just Dead or Just Different" addresses some of the inherent challenges in designing in a scaling environment. The organizers note "With the ongoing trend towards more and more digitization in applications ranging from multimedia to telecommunications, there is a big debate about whether there will remain a need for analog circuits in scaled technologies. Analog circuits do not seem to take advantage of nanometer CMOS; rather they suffer from it. So if the question is asked, "Will analog scale", you get conflicting opinions. One camp argues for an almost-all-digital future. Analog/RF content should be limited, because it's difficult, expensive, risky, and can be done with DSP. The opposing camp counters that some critical circuits simply do not want (or need) to scale, and analog is only "risky" when you let digital designers do it. So, what is the future role of analog circuits in scaled CMOS, and can analog EDA tools help in this?"

Looking for exhibitors with analog and mixed signal tools might be a challenge. Of the over 1200 products being exhibited, fewer than 70 are labeled as analog/mixed-signal/RF tools. Many of the products tend to defy simple categorization, so they show up in the infamous "other" category. Most of these tools come from smaller vendors, but you can go to the bigger vendors and try to find an applications engineer who talks “.model” or “.temp”.

To make the search a little easier, here is a list of companies with some type of analog design tool, in booth order. The list does not include the analog analysis capabilities required for the digital timing, EMI, and power analyses. Be sure to check the booth numbers at the show for last minute additions or transcription errors. For those mostly working with analog modules and higher-level models, the companies marked with a * have model creation and transformation tools.

Infinisim, Inc. (304)*, Lorentz Solution (324)*, Accelicon Technologies, Inc (623), Dolphin Integration (714), Mentor Graphics Corp. (928), Tanner EDA (1114), Ansoft Corp. (1128), Cadence Design Systems, Inc. (1228), Agilent Technologies (1706), Nascentric, Inc. (1824), Berkeley Design Automation (1924), Applied Wave Research, Inc. (2106), Lynguent, Inc. (2214)*, Syncira Corp. (2220), Infiniscale (2224)*, Kimotion Technologies Inc. (2302), Anasift Technology, Inc. (2322), Gradient Design Automation (2328), MunEDA-ChipMD (3028), Quintics (3314), Zeland Software, Inc. (3351), Synopsys, Inc. (3773), Knowlent Corp. (3955)*, Legend Design Technology, Inc. (4063), Orora Design Technologies (4251)*.

In the analog IC design space, outside of the merchant IC vendors, the tools and methodologies for design are changing to add speed, capacity, and higher levels of integration and automation. The greatest difficulty for designers is to determine whether the challenges of adopting the new capabilities are greater than the efforts to extend the existing design environment for at least one more generation of designs. For those going to DAC in San Francisco this July, it's a good opportunity to check out the latest tools.

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Speaking of Reality:

June 26th is the deadline for early registration. For all of those last minute shoppers among our readers, congratulations! You made it to the last few hours and, sadly for you, we are not holding an inventory closeout - in fact no further discounts, no additional grace period. So, drop whatever you are doing that is so important in your project and take a few minutes to register. It will help your budget and your manager will surely appreciate your sensitivity to the financial welfare of the department. You now have an additional reason to attend: if you have never heard Joe Costello speak, you are in for a treat. If you are an EDA veteran, it is already intriguing to speculate on what he will say. Go to
www.dac.com/43rd/reg.html and click on the REGISTER button.
See you there.

Berkeley Design Automation provides innovative circuit analysis tools that improve the design and verification of analog and RF ICs. Berkeley
Design's Precision Circuit Analysis (PCA) technology closes the analysis gap, the difference between what designers can accurately simulate using traditional tools and what is measured in silicon. PLL Noise Analyzer, the company's first product, is the only tool that accurately characterizes the noise of PLLs at the transistor level.

During DAC 2006, SynCira Corporation (booth #2220) will preview the industries first high-capacity, electrical performance driven hierarchical analog layout synthesis tool. With ease-of-use, fast turnaround, and true concurrent analog design and layout generation, the analog circuit designers can now generate analog layouts optimized with 100% constraint satisfaction. Placement, routing, parasitic extraction, back annotation and GDS-generation are integrated. Please visit our website www.syncira.com for more information.

ACM's Computing Reviews is the authoritative publication of reviews in computing literature, and our reviewers provide the expert commentary needed to find out what is new and worth reading. To apply to become a reviewer, go to http://www.reviews.com/reviewer and click Become a Reviewer.