Conference Program     At-a-Glance    Wednesday


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WEDNESDAY
Exhibit Hours - 9:00 am to 6:00 pm
Rm# 306/308 307 305 304 303 301
Ses# Session 16 Session 17 Session 18 Session 19 Session 20 Session 21 HoT
TIME Pavilion
Panels
9:00  
9:15  
9:30  
9:45  
10:00 Student Design Contest Award Presentations
10:15
10:30
10:45
11:00  
11:15 The Xbox 360 Uncloaked: Doing What it Takes to get Chips into High-Volume Consumer Electronics
11:30
11:45
12:00  
12:15  
12:30  
12:45  
1:00 AMD and DreamWorks - Fueling Technology Innovation
1:15
1:30
1:45
2:00  
2:15 ESL: Software Engineers Are from Pluto and Hardware Engineers Are from Mercury: Can ESL Bridge the Gap?
2:30
2:45
3:00
3:15  
3:30  
3:45  
4:00 The Accidental Pirate (organized by the EDA Consortium)
4:15
4:30
4:45  
5:00  
5:15  
8:30 to 10:00

 

Special Session: MPSoC Design Tools

 

Buffer Insertion

 

Testing and Validation
for
Timing Defects

Advanced Topics in Processor
and
System Verification

 

Software
for
Real-Time Applications
BREAK 10:00 - 10:30 am
Ses# Session 22 Session 23 Session 24 Session 25 Session 26 Session 27
10:30 to 12:00

 

PANEL: Building a Standard ESL Design and Verification Methodology: Is It Just a Dream?

Invited Session:
CAD Challenges for Leading-Edge Multimedia Designs

 

Routing

 

The Test Bin

PANEL: Variation-Aware Analysis: Savior of the Nanometer Era?

 

Low Power and Ultra-Low Voltage Design
LUNCH 12:00 pm - 2:00 pm
Ses# Session 28 Session 29 Session 30 Session 31 Session 32 Session 33 HoT
2:00 to 4:00

 

High-Level Exploration and Optimization

PANEL: Design Challenges
for
Next-Generation Multimedia, Game and Entertainment Platforms

 

CAD
for
FPGAs

Secure Systems

 

Logic
Synthesis 1

Low Power, Thermal-Aware Architectures
BREAK 4:00 - 4:30 pm
Ses# Session 34 Session 35 Session 36 Session 37 Session 38 Session 39
4:30 to 6:30

 

Low Power System Level Design

Power-Constrained Design for Multimedia

Electrical and Thermal Issues in FPGAs

Special Session: Beyond
Low Power Design: Environmental Energy Harvesting

 

Communication-
Driven
Synthesis

 

Parallelism and Memory Optimizations