44th Design Automation Conference, June 4-8, 2007

May 30, 2007  


Just Announced:  DAC Goes Mobile!  A mobile version of the DAC web site was launched yesterday to make it easy for you to access conference information from your mobile device.  Check it out at: www.dac.com/mobile

The Overture

Gabe Moretti, Editor

Just like a symphony, a leading conference needs an overture to set the tone for the coming experience.  For many years, Dataquest provided the melody that got attendees into the DAC mood.  The EDA Consortium (EDAC) has taken over the baton and will host the industry reception, with co-sponsorship by EDN Worldwide and the TSMC Design Ecosystem.


This popular kick-off reception will be an industry-wide welcome to DAC and will provide an opportunity to reconnect with a diverse group of colleagues from the electronics design community. The evening will feature a head-to-head discussion between two industry panels — a customer panel and a vendor panel – and will reflect attendees’ input. One panel will consist of executives from companies designing advanced chips, and the other of technical executives from companies in the TSMC design ecosystem — providers of EDA design tools, libraries and IP, and design services.


Entitled “Design Challenges: A Real-time Reality Check,” the panels will focus on the different categories of new chip design challenges to be encountered over the next two years. It promises to be a lively and entertaining evening that should provoke further discussion. 


Ron Wilson, executive editor EDN Magazine, and Ed Sperling, editor-in-chief Electronic News, will moderate the panel discussion. The dual-panel will include representatives from such chip-design powerhouses as Broadcom, eSilicon, National Semiconductor, and Qualcomm and major infrastructure vendors including Analog Bits, ARM, Magma, Synopsys, and TSMC. The event is jointly sponsored by EDA Consortium, EDN Worldwide, and members of the TSMC Ecosystem including Analog Bits, ARM, eSilicon, Magma, and Synopsys.


The event will be held at the San Diego Marriott Hotel, Marina Ballroom, 333 West Harbor Drive, Sunday June 3. The reception will begin at 5:00 p.m. and the panel discussion at 5:45 p.m.  Registration is complimentary. Register for the EDAC Reception.


Following this network opportunity, Gary Smith EDA (GSEDA) will host another event beginning at 7:15 p.m.  The company will continue DAC’s traditional Industry Report with the latest industry trends and information that affects design flows.  The program is as follows:


Tom Starnes

"Multi-core Processor Considerations in Modern Day SoC Designs"


Mary A. Olsson

"What EDA and Chip Designers Don't Think About"


Daya Nadamuni

"The Crisis in Software Programming: How to Prepare for Multi-core"


Gary Smith

"Alive and Well but Software Challenged"


The GSEDA reception will begin at 7:15 p.m. and the presentations at 7:45 p.m.  The event will be held at the San Diego Marriott Hotel in the San Diego Ballroom Salon B.  To register for this event go to: http://www.garysmitheda.com/.


Both of these events will enhance your DAC experience and provide you with the opportunity to reunite with colleagues, meet known and new vendors, and exchange those new business cards you have had printed just in time.

DAC: A Concert of Symphonies

Gabe Moretti, Editor


The Design Automation Conference offers a wide menu of events to its attendees.  The tutorials, workshops, management seminar, and other activities organized by companies and consortia combine with the technical program to offer six full days of informative and, at times, entertaining events.  The San Diego Convention Center will be the center of activities from June 3 to June 8 and will provide everyone involved in designing electronics products or tools to support such activities with topics they can learn from.  In addition, the Exhibit Floor is the only place where you can find the largest number of EDA and semiconductor companies in one place.  Walking the exhibit floor, either with the purpose of seeing specific vendors, or browsing to find new tools and applications, or just looking for the vendor with the most desirable give-away, you are bound to learn something new about EDA and about the design methodology.


Designers wrestling with issues related to 65nm processes and contemplating life at 45nm will find interesting topics and tool proposals, but also those developing consumer products at 130nm can find plenty of interesting ideas and tools.


Verification issues continue to be of paramount importance, no matter the nature of the design.  Whether you are doing a mixed-signal design at 130nm, or an SoC manufactured at 65nm, there is still a lot to learn in verification and validation and plenty of vendors willing to show the latest tool and trend. 


The Technical Program also offers an opportunity to hear what other people are doing, whether you are interested in exploring the ESL space, or want to learn some new design methods that will ease the validation effort.  For example, stop by The Mathworks booth and talk to them about how the automotive industry established a standard for Simulink models in order to improve coverage and decrease time for design validation.  This is something you would not likely hear from just talking to a traditional EDA vendor.  Comparing what other industries are doing often gives new ideas to the electronics professionals.  And of course, we give as well as we receive.  Go listen to the keynote speech on Thursday. Prof. Jan Rabey will speak about the late Richard Newton's foresight in applying EDA methods in the field of biology, chemistry, and physics.


At DAC, you can hear about mixed-signal design issues and how they are being solved and what still remains to be done.  The analog world is a noisy world and some of the fault is its digital neighbor.  This is true even for printed circuit boards, not just for leading-edge designs.


The conference theme - Automotive Electronics may have given you cause to pause.  You probably do not work in the automotive field, or work for an EDA company that thinks it has no automotive customer.  But, in fact, the variety of designs, done to support the development of a modern car, cover just about every aspect of EDA.  And, the customer developing a DSP, a cell phone, or many other digital and mixed-signal ICs or IP blocks may in fact be an automotive sub-contractor.  It would be unwise to pass up the opportunity to discover new facts, explore new business and professional opportunities just because the automotive subject has never come up before in conversation.


The Management Seminar has been one of the most successful events since its inception a few years ago.  This year, the program deals with innovation, the primary engine of EDA.  It offers a unique opportunity to hear Dr. Geoffrey Moore, a best selling author and managing partner at TCG Advisors.  He will be joined by Raul Camposano and Rohit Sharma in exploring various aspects of innovation in our industry.


I found that although the event is marketed primarily to managers, you do not need to be one to attend.  As you plan your career growth and plan to become a manager some day, you need to prepare and take advantage of the opportunity to experience what your boss and her boss worry about, talk about, and learn about.  It is never too early to prepare for the major shift that the jump from designer to manager is.  As a manager, you need to think differently, evaluate new issues, and solve different and more heterogeneous problems.  Take the opportunity and experience the management environment in an event that allows you the freedom to explore and develop approaches without the cost of making the wrong decision.  And, it is also a smart career move: someone who counts may be there and assume that you must be "management material."


Being an electronic engineer means that you never stop learning.  Four workshops on Sunday, two tutorials on Monday and five on Friday, give you a chance to improve your knowledge and explore new fields.  The Sunday workshops' subjects range from UML for SoC design, to hardware dependent software, while the other two deal with designing low power circuits.


On Monday, you can hear about issues dealing with variability and issues regarding the design of products for multimedia applications.


Finally, Friday gives you the opportunity to attend tutorials on formal assertions, packaging, the source and cure of soft errors, the impact of manufacturing on yield, and more about low power circuits.


As you can see "Power" is the issue.  Traditionally, one would think that it is just about how to limit the use of power in both portable and stationary systems.


I prefer to think that DAC deals with your power: the power to be informed, to improve yourself professionally, to expand and improve the network you depend on as a tool to better your career.


Starburst-Register Today


DAC Quick Links


Apache, the leader in power signoff and the provider of silicon integrity platform for SoC, analog-IP, and system designs will be hosting customer presentations at DAC booth #6382.  Designers from Broadcom, Cisco, LSI, ST, and TI will discuss how they are addressing power, leakage, timing, reliability, and IC-package challenges. Space is limited so register today to reserve your seat!

Denali Software, Inc.

Visit Denali at DAC! Booth #6060

Denali experts will be on hand to demonstrate our complete line of Design IP, Verification IP, Embedded Software, and SystemVerilog solutions, including:

     * Design and Verification IP for: PCI Express 2.0 and IOV

     * Memory Controller & PHY IP for: DDR1,2,3 and LPDDR DRAM

     * HW/SW IP Platform Solution for: MLC NAND Flash

     * and complete verification IP for your SystemVerilog migration, including: AMBA, DDR, Flash, PCIe, PLB, SATA, USB, & more...

Schedule a meeting today: http://www.denali.com/dac2007.html

EDA Consortium & FSA

Don’t miss the all new, Productivity Impact Luncheon - Changing the Dialogue between Engineers and Management.  Held in conjunction with the 44th DAC Management Seminar, the luncheon program will draw from research and practical examples to examine key factors impacting engineering productivity, including communication pitfalls between engineers and management.  Register for the Productivity Impact Luncheon. 



     • Metric Driven Design Verification - Carter & Hemmady
     • DFM and DFY for NanoScale CMOS - Chiang & Kawa 
     • SystemVerilog Gotchas - Sutherland & Mills
     • Hardware Verification with SystemVerilog - Mintz & Ekendahl


     • Low Power Methodology Manual - Keating, Flynn, Shi, Gibbons & Aitken
     • Modern Circuit Placement - Nam & Cong
     • Closing the Power Gap Between ASIC and Custom -- Chinnery & Keutzer

Tanner EDA

Tanner EDA, the leader in affordable, portable analog/mixed signal IC design tools invites you to Booth 4873. Visit our technical experts for a demonstration of the performance enhancements of T-Spice, our simulation and verification tool. L-Edit, our physical design tool, as well as HiPer, the only hierarchical, foundry-compatible DRC tool on the market. Come join us!