Thinking Too Small
Are Analog Designers Secret Luddites?
by Geoffrey James
The dream is compelling. Rather than monkeying around at the Register Transfer Level (RTL), designers will someday work at the Electronic Systems Level (ESL) using a language like SystemC. The ultimate goal, of course, is to allow designers to create a true System on Chip (SoC) which contains all the circuitry and "software" needed to support an entire product. Gone will be the busy-work and tweaking that's part and parcel of chip design. Making SoCs will be simple and easy.
There is only one thing wrong with the dream: it is not going to happen -- at least, not unless something changes when it comes to designing analog and mixed signal. The sad truth is that after years of attempted automation, designing analog and mixed signal remains a "black art." And that's becoming even more true as chip manufacturing processes move to 65nm and 45nm. At the smaller geometries, analog and mixed signal are so difficult that some designers are opting to put the analog on a separate chip. And that's a trend that (if it becomes truly popular) could keep the ESL/SoC dream forever in dreamland.
However, some industry analysts believe that some of the problem lies not in the difficulty of analog design but in the fact that analog designers are being difficult. "They have always prided themselves in their ability to squeeze that maximum performance out of their design, whether they need to or not," complains former Gartner analyst Gary Smith of Gary Smith EDA. As we move to the sub 90nm nodes, it's fair to ask: might the failure to automate analog design be the result, if only in part, of an engineering culture that disdains automation just as Luddites opposed the introduction of machinery in manufacturing?
Little Big Problems
There's no question that, from the viewpoint of physics, analog circuitry poses major difficulties at the smaller geometries. As the component size gets smaller, designs that worked at the larger geometries no longer function predictably. The physical proximity of circuit elements and the thinness of the "insulation" tend to augment the effects of inductance, capacitance and leakage. As a result, analog design processes typically involve a great deal of crafting and re-crafting before products can be expected to run correctly, according to Robert B. Pease, NSC's famous analog design guru.
These challenges grow worse as the geometries get smaller, according to Dave Robertson, a product line director at Analog Devices, Inc. in Norwood, MA. "Designers will have to be prepared for more 'surprises' as the architecture is taken down to the transistor level," he says. Dave also believes that using ESL to generate SoCs is something of a red herring. "The future of chip design isn't going to be software coders who back off three notches and handle everything at a high level," he insists. "Electrical engineers will continue to have the primary place in chip design."
The problem is exacerbated by the fact that, when it comes to analog and mixed signal, RTL automation has proven disappointing. "As much as we wish it weren't the case, the EDA industry really hasn't been able to do that much to help automate the analog design process," mourns Ashutosh Mauskar, vice president of product and business development at Magma Design Automation. "There is simply no practical way that I can currently replace the best analog designers with an EDA tool."
It should be pointed out that the purpose of EDA has never been to replace an engineer with an automated tool. Instead, the goal is to develop tools that increase the productivity of both digital and analog designers. The fact that EDA vendors have so far lagged in helping analog designers may be the result of not enough "out of the box thinking." It may be necessary to explore a new analog design methodology, not just new tools that mirror the methods used in digital design or that attempt to replicate manual analog design processes.
EDA tools don't address analog designs effectively because "every circuit needs to be designed to a level of near perfection," continues Mauskar. "It's like you're a car company but the only kind of car that actually works is a Ferrari. Something less polished, like a Toyota, simply isn't good enough to get on the road." Under the circumstances, it's not surprising that the complexity of analog design looks likely to scuttle the dream of a fully automated analog/digital design environment to create SoCs through ESL. Or so says conventional wisdom.
Overestimating the Difficulty
But is conventional wisdom actually correct? Some analysts are beginning to express suspicions that analog designers may be inflating the difficulty involved in creating workable analog circuits. For one thing, analog designers have been complaining about smaller geometries for so long that their complaints begin take on an aura of crying wolf, according to Jordan Selburn, principal analyst at the semiconductor market research firm iSuppli. "Ten years ago when I was at Gartner, there was speculation that true SoC would be just a passing trend because there wasn't parity between the digital and analog real estate," he remembers.
Gary Smith points out that analog designers have always been a conservative lot, insisting that their craft was so unique and so special that it essentially trumped the complexity of other aspects of chip design:
"The first SoC analog crisis came when we moved to 180nm. DATE was full of papers and presentations on how the 250nm analog section of an SoC would soon take up a majority of the chip area as the digital section of the SoC moved to 180nm and below. 250nm was considered the smallest geometry you could use for analog. At the next DATE ST introduced 180nm analog circuits. We are now doing 90nm analog and I've seen some 65nm analog."
Despite the dire predictions, EDA vendors have been able to overcome the barriers that once loomed so large, according to Navraj Nandra, Synopsys's director of product marketing for mixed-signal IP. "We're developing IP that goes into digital CMOS and focusing on submicron designs that use much lower supply voltages," he explains, "These circuits have to work easily and well because we deliver them as IP to customers who don't want to worry about these complex design issues."
System houses have also found ways to achieve analog/digital integration using a common footprint, albeit not on the same die. System-in-Package (SiP) and 3D integration allow designers to minimize PC board area using available vertical space.
Richard Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research Corp., notes that analog circuitry on SoCs at 65nm have indeed become both possible and usable. "This analog IP is characterized to operate at the low(er) voltages that 65nm requires," he explains. While Wawrzyniak admits that "there may be performance issues in running the analog in 65nm at the lower voltages as opposed to running it at higher voltages like 3.3V or even 5.0V," he points out that the usability of such circuitry "depends on the application and what kind of performance is needed."
What's important here isn't so much whether it's possible to do analog effectively at 65nm, but that there was so much controversy and resistance to the idea amongst analog designers. If they're capable of overstating the difficulties of moving to smaller geometries, might they not also be overestimating the difficulty of automating more segments of the analog design process? In other words, might there be some unconscious (or even conscious) resistance to the idea that analog design might not be the "black magic" that the designers make it out to be?
Hard Design or Easy Money
If so, there are plenty of financial reasons to support the status quo, because analog design is one of the most profitable segments of the semiconductor industry.
First, there are the astronomical salaries. And since many analog designers were trained back when universities still had extensive analog design programs, it's not unusual to find analog designers with decades of experience. According to a survey conducted in 2005 by the recruiting firm The Analog Group, an analog/mixed signal design engineer with as little as 16 years experience can earn as much $233,000 a year (including bonuses and stock). That's far more than the salary of, say, a software engineer trained in the 1960s. When was the last time you saw a big salary offered for experienced COBOL programmers?
Second, there are the very attractive profit margins. You'd think, given the high salaries, that firms specializing in analog design might struggle to make money. But you'd think wrong, because chip companies that concentrate on analog are, in general, far more profitable than their digital-focused counterparts, according to Risto Puhakka, vice president at the analyst and consulting firm VLSI Research. The latest annual report from Analog Devices, for example, shows that profit margins for its analog product line are around 24%. Linear's margins are a record 37%, while National profits in the analog segments are just below 20%. Puhakka notes that if an outside firm actually succeeded in automating analog design, it would pulverize the high margins and high salaries. "There could be, and probably are, proprietary techniques inside some of these firms that aren't being shared with the outside world," he says.
Interestingly, some EDA firms have pretty much thrown up their hands when trying to convince the analog priesthood to change their ways. "Automation is possible but it's very difficult to change the methodology for analog designers because they are stubborn beasts for the most part," says Synopsys product marketing manager Mike Demler.
Similarly, Gary Smith believes that some of the perfectionism associated with analog design is more the result of culture than technical necessity. "When I was employed at Telmos, we found that we could do 85% of the designs with what became known (unofficially of course) as good enough analog," he says, "The guys that bought it were engineers that use analog to solve a problem when appropriate [but the] engineers in the analog group wouldn't touch it." Gary's experience at Telmos seems to contradict what Magma's Mauskar states. But it is likely that EDA vendors are presented only with the most difficult of analog design problems, since the majority of designs, as in Gary's experience, would not warrant the investment in new EDA tools.
This is not to say that there's some kind of explicit conspiracy going on. That would be paranoid even to suggest. However, it's not paranoid to point out that analog designers, and the firms that employ them, have a vested interest in keeping the mysteries of analog design, well, mysterious. And that could be delaying the actual advent of the ESL/SoC dream.