Contributing Editors: Peggy Aycinena, Geoffrey James, Gary Smith, Ed Sperling
Editor-in-Chief: Gabe Moretti
|vol.3 / issue 4 December 6, 2007|
IN THIS ISSUE:
Peggy Aycinena interviews Yervant Zorian
I would like to begin by wishing all of you Happy Holidays. May you find peace within yourself, within your family, and on this small, yet so complex, planet we call home.
We have three interesting articles this month. The newest member of our editorial staff, Ed Sperling, writes about the opportunities and obstacles presented to EDA vendors by the wireless segment of the market. I must confess that some of what he writes comes as a surprise to me, and yet I am supposed to be up to speed on EDA!
DACeZine Editor Wins Meritorious Service Award
by Karen Bartleson
By Dennis Brophy
DACeZine Editor-in-Chief, Gabe Moretti, was honored recently with the Ron Waxman Design Automation Standards Committee (DASC) Meritorious Service Award from IEEE, the first recipient of this yearly honor.
The award recognizes commendable accomplishments by DASC members, and Moretti’s contributions exemplify the spirit that we’d like to recognize and encourage in serving DASC. He helped move DASC beyond its original VHDL-only focus, making it an organization for EDA standards with a wider and more compelling scope. By teaming with others, and being willing to set and enforce higher standards, Moretti has helped DASC to do much more than it would have without his encouragements.
As an early DASC pioneer, Moretti has delivered a high level of service over many years. Among other activities, he was a contributor to VHDL 1076 and Verilog 1364, chair of both the VHDL logic package 1164 and the OMI Modeling standard working groups. He actively promoted corporate standards helping bring the DASC to a new level; this had the effect of greatly rejuvenating the DASC.
DASC is responsible for the standardization of Design Automation related standards in the IEEE Standards Association. This award is named for Ron Waxman, a founder of DASC, in recognition of his many years of leadership and service to IEEE and international standards.
DAC and the DACeZine are tools you can use in growing your awareness of the industry and the possibilities it offers. I hope the publication can stimulate new ideas and new approaches. Continue to write: your feedback helps us improve. Send your letters to: email@example.com.
And tell your friends to subscribe to DACeZine as well -- it is a very good way to get ready for the next DAC in Anaheim. They can do so by visiting the www.dac.com web page.
Yervant Zorian: Grand Master of Time Management
by Peggy Aycinena
When you talk to Yervant Zorian, there's one question that comes to mind: Is it the journey or the destination? He runs so fast and balances so many responsibilities simultaneously, one would think it's the multiple end points that are his motivation. But, look again. Yervant Zorian is not waiting for the end of the journey to validate the worth of his many parallel paths. For this marvelous technologist and industry leader, clearly each and every step along the way is a joy. This is a man who loves life and embraces the journey as much as, if not more than, the destination. How else could he remain so positive in the face of so many overwhelming obligations?
As Vice President and Chief Scientist at Virage Logic, Zorian helps set direction for the company and manages an extensive, far-flung R&D team. But that's only his day job. Currently, he also heads up the Exhibitor Liaison Committee for the Design Automation Conference and is organizing the Management Track for DAC 2008 in Anaheim, Calif.. He has had, and continues to have, multiple assignments related to the Design Automation & Test Conference (DATE) in Europe. He just finished running the second annual two-day DFM&Y Workshop at the International Test Conference (ITC) in Silicon Valley in collaboration with U.C. San Diego's Andrew Kahng, while also participating as always on the ITC Steering Committee itself. Previously, Zorian served as vice president of the IEEE Computer Society responsible for Conferences and Tutorials, and continues to be active with that group. He was also long-time editor-in-chief of the IEEE Design & Test magazine – virtually a full-time job in itself –- while juggling that role with his work in industry. He continues on in an emeritus capacity with Design & Test today. He also continues, as he has for many seasons, as chair of the IEEE 1500 Standardization Working Group.
Over the years, in and around all of this, Zorian has authored over 250 papers, written four books, organized countless panels, given a plethora of technical talks with an emphasis on his expertise in self-test (his Ph.D. in EE is from McGill), raised a family, and traveled the globe. Last week he was at IMEC in Belgium. This week he's in Silicon Valley. Next week he's in Japan. Hence, Yervant Zorian is not only a Fellow of the IEEE and winner of both the IEEE Industrial Pioneer Award and the Hans Karlsson Award, he's also the owner of countless Frequent Flyer Miles. It's a miracle that he had any time to speak with me at all, but speak he did – with his distinctly upbeat point of view – first about DAC and then about time management, a skill he thoroughly mastered a long ago.
Management Track at DAC 2008
"At DAC, I have a dual responsibility," Zorian told me. "On the one hand, I'm heading up the Exhibitor Liaison Committee, which includes some level of coordination across that committee and the Strategy Committee. The other piece of my DAC responsibility is assembling the special Management Track. This will be completely different from the Executive Track that you may be familiar with from DAC in the past, or from DATE. Those events were created to attract additional senior executives to the conferences. This Management Track at DAC is for mid-level managers, not senior executives. The intention is to discuss actual projects and the decisions these managers must make at every step along the way under very difficult circumstances.
"As we all know, designs today are quite complex because of the level of integration, and because of the many different options presented to product managers over the course of a project. Selecting tools and a foundry, making a series of decisions about IP choices, whether to access third-party design service or use internal development, and which packages to use –- these are among the many difficult choices presented to the manager. Our special Management Track at DAC will address these choices, and will include six or seven managers from different companies in charge of various types of projects speaking about the decisions that go into creating these very complex, state-of-the-art chips."
Zorian added, "With help from our colleagues, we are working through various channels in the industry to identify the managers who will be invited to give a series of 30-minute talks during this special track. These speakers will represent different classes of chips – cellular chips, graphics chips, etc. –-because the needs and processes can vary widely between classes."
"Traditionally, DAC has provided a lot of opportunity to discuss both commercially available EDA products and leading-edge research from academia. This new track falls into neither of those categories. The Management Track at DAC is intended to address questions like: How do you partition a design when the chip will be designed in three different continents? How can you make sure all of the pieces will come together smoothly? How do you pick the right tools, IP, foundry, and process node appropriate to your design? DAC has always included papers that address the technical challenges of design, but this type of real-world discussion will be new in the 2008 Management Track."
It's the Content...
I recently went to an office supply website looking for a roll-about cart for my laptop. At this site, there were four models, each with various "customer reviews." The overall scores ranged from 3 (out of 5) to 5. "Maneuvers well," said one reviewer. Another review said, "Difficult to maneuver." "Can handle heavy loads", said one, while another said, "Can't handle heavy loads." How to choose? All four models were from the same manufacturer. The only difference between the four models was the color. There was no lack of words describing people's thoughts on this product, but not much useful information. After visiting the site and reading the reviews, I am no closer to deciding if I want to spend my money on this product or not.
For years, the EDA trade press has been a trusted source of news and information related to electronic design. In an effort to attract and retain readers and increase value to advertisers, EDA publications hired qualified editors and writers to assure that the information published in their name was accurate, relevant, and informative. Readers knew the qualifications and evaluation criteria of each editor and writer, and this helped the engineers to reach a more objective conclusion.
In the example, the small amount of useful information on the website was: 1) that the product existed, 2) a photo, and 3) a few basic facts, such as height and shipping weight. This is equivalent to the ads in the trade magazines. Chip and system designers must first be made aware that a product exists or they cannot begin to evaluate its applicability to their problems. The decision to evaluate and purchase a new tool is ultimately greatly influenced by engineers who have relied on the EDA press as a trusted source -- to help determine what new products or services are potentially worth their limited time to evaluate, and as an aid in understanding how new tools and techniques could help get their next product out the door with less headaches than the last one.
Spotty Connections in WirelessEDA vendors view market as big growth opportunity, but gaining a firm foothold is proving harder than expected.
by Ed Sperling
Wireless may look like a vast, untapped market opportunity for EDA vendors, but so far it hasn't proved to be a particularly lucrative one.
This is especially frustrating to the EDA industry, which prior to the 2001 downturn was considered a bright spot in a maturing electronics industry. But growth has been lackluster since then, leaving EDA vendors with two options --sell more tools to existing or new customers, and find new markets. They are taking both approaches very seriously.
Need for Proprietary Advantages
"We were the first to introduce Viterbi acceleration," said Carson. "We are certainly open to using outside tools, but in-house we have developed highly differentiated things. If something is considered a commodity, we're better off procuring that externally. We look a lot at make versus buy, and we do try to buy tooling because we would rather have our personnel working on things like 4G cell libraries."
That leaves the door open for standardized intellectual property (IP), but Carson said it would be harder for EDA vendors to make inroads in the core acceleration algorithms.
EDA vendors discovered this conundrum at the end of the last decade, when both Mentor Graphics and Cadence released their first tools aimed at the wireless market. Both were hailed as major breakthroughs by the companies that made them but sales were weak. Since then, Mentor and Cadence have upped the ante in places where they perceive the opportunities to be in the wireless market.
DAC Student Design Contest Seeks Industry Support
DAC is seeking industry sponsorships for this year's Student Design Contest. Last year's corporate supporters included Cadence Design Systems Inc., IBM Corp., Intel Corp., Mentor Graphics Corp., Mindspeed Technologies Inc., Synopsys Inc. and Tanner EDA and industrial support from the Semiconductor Research Corporation (SRC). Support also came from DAC sponsors: the Association for Computing Machinery (ACM) Special Interest Group on Design Automation (SIGDA), IEEE Council on Electronic Design Automation (CEDA), and the IEEE Circuits and Systems Society(CASS).
The prestigious annual Student Design Contest, jointly sponsored by the DAC and the International Solid State Circuits Conference (ISSCC), promotes excellence in electronic systems design and is made possible through the contributions of corporate sponsors. Winners will be recognized in an award ceremony to be held during DAC, June 8 – 13, 2008 at the Anaheim Convention Center in Anaheim, Calif.
"The Student Design Contest encourages innovative research that integrates all aspects of design, from system-level design to tools, methodologies and implementation. Students that have participated in the contest have always greatly enjoyed it and felt it was an important milestone in their careers," said Limor Fix, general chair, 45th DAC Executive Committee.
This year’s Student Design Contest co-chairs are Bill Bowhill, senior principal engineer at Intel Corp., and Byunghoo Jung, assistant professor of Electrical and Computer Engineering at Purdue University.
“The DAC/ISSCC Student Design Contest presents graduate and undergraduate students with a unique opportunity to be recognized for the meticulous research work they have completed during their studies,” said Jung. “At the same time, the contest presents the EDA industry with the opportunity to see what the future leaders of the industry are doing.”
The total prize money is expected to be more than $20,000, shared among 10 design award recipients. Winners will be notified prior to the 45th DAC and offered travel assistance to attend.
Winning submissions will be displayed as posters at the DAC University Booth on the exhibit floor. Selected winning entries may be included in the Technical Program, at the discretion of the Technical Program Committee. Winners will also be invited to present at a special poster session at ISSCC 2008 to be held in February in San Francisco.
Forward to a Friend
|visit us at |