Contributing Editors: Peggy Aycinena, Geoffrey James, Gary Smith, Ed Sperling
Editor-in-Chief: Gabe Moretti
June 8-13, 2008, Anaheim Convention Center, Anaheim, Calif.
|vol.3 / issue 10 April 17, 2008|
IN THIS ISSUE:
Ed Sperling, Transaction-level Verification
Luc Burgun, EVE
Using a Bit of French-Inspired Creativity to Navigate the Silicon Valley Magic
Since the fall of the Roman Empire, France has played a key role in the molding of western civilization. In the ninth century, Charlemagne, a Frank, unified Europe leaving a legacy that resonates to this day—after all, he is called The Father of Europe.
While Italy had been the cradle of the Renaissance, it was 16th-century France that promoted it to the European level, invigorating all forms of the arts. The Age of Enlightenment followed by the Age of Reason have been remarkable French movements with far-reaching implications throughout the western world. The French Revolution laid a stone on the aristocracy and opened the door to the emergence of the bourgeoisie. Napoleon Bonaparte may have inflicted considerable pain on his European neighbors, but he also fathered the Napoleonic Code, a major step in establishing the rule of law in many other countries.
In every field of human endeavor, whether science or philosophy, art or medicine, law or administration, the French have left an indelible mark and implanted a strong influence on our way of life.
45th DAC Program Now Available on the website.
Register on or before May 19th and receive 20% off Conference Registration or for a FREE Exhibit Pass!
Register on-line today!
The Pace Quickens as we Approach the Opening of the 45th DAC
by Gabe Moretti, Editor
Companies continue to try to catch problems as early as possible in the design cycle. DACeZine organized a roundtable discussion about system-level verification to explore the topic. The article on Transaction-Level Verification gives a picture of the thinking about some of the issues associated with this topic. To be fair, the technology is still new, and a few of the approaches are experimental. But the requirements are concrete and the development of the TLM 2.0 specification by OSCI is an answer to the need.
Simon Davidmann brings the software point of view, while Lauro Rizzatti speaks from an emulation background. Patrick Sheridan has been involved with ESL issues for some years and has also been instrumental in the growth of OSCI. Finally, Giovanni Mancini from The Mathworks provides the experience of a company that has dealt with system design issues not just for electronic design, an area they are entering with enthusiasm and success, but also at the level of integrating and verifying heterogeneous systems.
Luc Burgun, CEO of EVE, the successful emulation company based in France, provides a humorous view of what it is like to start a company outside of Silicon Valley. At times you may think that his view of the role of France in the world's affairs may be a bit parochial, but we must confess that Silicon Valley suffers, frequently, from the same malaise.
The third article looks at the immediate future of the EDA business as it is affected by Moore's Law. Geoffrey James gives reasons to dismiss the predictions of those who say that manufacturing complexity will constrain creativity and force designers to use standard logic blocks that have been pre-verified by the foundry. I am in the camp of those that say that some standardization will occur, especially in analog design.
The DACeZine also has a Letters to the Editor section to allow for shorter contributions to the contents and directions of the publication. When necessary, answers to the letters will come from the appropriate member of the team (including our readers), since I do not (yet) hold the total knowledge of the industry within me. I encourage all of you to write, either a viewpoint or a letter, and state your opinions on matters that impact our industry, the contents of this publication, or, for that matter, the publication itself. Send your letters to: email@example.com.
DACeZine sat down to discuss transaction-based verification with Lauro Rizzatti, general manager of EVE USA; Patrick Sheridan, director of solution marketing platform design solutions at CoWare; Simon Davidmann, president and CEO of Imperas; and Giovanni Mancini, product marketing manager at The Mathworks. What follows are excerpts of that conversation.
By Ed Sperling
Q: Transaction-level verification (TLV) is a term that sounds very precise, but the real-world application seems far less so. What exactly does it purport to solve?
Rizzatti: TLV is a way of simplifying the testbench and moving out everything that is time-consuming because it is at a lower level of abstraction. You only leave in the testbench the code that has to do with a high level of processing. This environment can work anywhere—in an emulation system or a simulation system. In terms of processing, it doesn’t matter which one you use. The simulator takes charge or the emulator takes charge of the testbench.
It’s been called the nightmare scenario for the EDA industry, and it goes something like this:
As the usable real estate on a chip (measured in terms of available transistor count) grows geometrically larger, the cost of designing a custom ASIC grows as well. Since each process node mandates additional design rules, that cost accelerates, particularly in the areas of test and verification. At some point, it becomes more economically viable to simply slap every kind of circuit that anybody might need onto a standardized, ultra-densely populated “platform” SoC, rather than to design custom ASICs. A relatively small selection of these programmable chips, manufactured at high volume and high yield, largely supplant the ASIC. As a result, the market for EDA software shrinks to a tiny handful of standardized platform SoC designers, thereby devastating EDA industry revenues.
There’s only one thing wrong with this idea: it ain’t gonna happen. Here’s why.
Reason #1. Design costs aren’t really rising all that fast.
DAC Workshops and Collocated Events
by Gabe Moretti, Editor
As in previous years, DAC attendees will have the opportunity to attend a number of events organized during the conference that address specific topics from across the ecosystem of electronic design. The number of events available this year is greater than ever before. By going to the DAC website and choosing Related Events on the left hand side menu, you will be presented with three choices: Collocated Events, Adjunct Events, and Additional Meetings. As I write this article, I count 25 events, mostly concentrated on Sunday and Monday, the two days preceding the opening of the Technical Program. But I dare say that the number is likely to increase. Additionally, a number of consortia, EDA vendors, and standards organizations are planning events during breakfast or lunch during the actual conference. You can find a description of each event by clicking on the appropriate link that is available from the DAC site, and the list is growing, so visit frequently to keep up to date. Workshops are listed under the Conference Program entry on the same menu.
Collocated events provide DAC attendees with the opportunity to attend specialized programs in specific areas of interest, and also give professionals attending them an opportunity to attend DAC while minimizing travel expenses and shortening the time spent away from their desks. The organizers of one of the events sent me additional information that I am happy to share with you.
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