Contributing Editors: Peggy Aycinena, Geoffrey James, Gary Smith, Ed Sperling
Editor-in-Chief: Gabe Moretti
June 8-13, 2008, Anaheim Convention Center, Anaheim, Calif.
|vol.3 / issue 7 March 6, 2008|
IN THIS ISSUE:
Geoffrey James, Automatic Analog Design
Up-Coming Submission Deadlines:
DAC Adds Exhibitor Forum to Line-Up
DAC has added the DAC Exhibitor Forum to expand the availability of practical and technical content to attendees and offer exhibitors an opportunity for increased exposure.
Presentations can address a wide spectrum of topics, including system-level design/embedded software, physical design, verification, power management/signal integrity, analog/mixed-signal/RF, DFM and IP cores. This exciting new forum features sessions devoted entirely to a specific domain such as verification with up to three companies presenting per session, followed by a short question and answer period.
DAC Partners with Global STC Conference
DAC has formed a conference alliance partnership with the Semiconductor Test Consortium (STC) to make the 45th DAC and STC’s Third Annual Global STC Conference (GSC) adjunct conferences. (See Guest Commentary by Keith Imai, GSC’s chairman.)
This year, DAC and GSC will be held in close proximity to each other and within the same time period. GSC will take place at the Hilton Hotel, San Diego Mission Valley in San Diego, Calif., June 4-6, and the 45th DAC will take place the following week at the Anaheim Convention Center in Anaheim, Calif., June 8-13. Additionally, the organizing committees of DAC and GSC are working together to provide additional value to their attendees through joint promotional activities and technical program synergies.
“We are excited to make GSC an adjunct conference of DAC, and expect that our complementary events will draw an expanded audience by being timed and located conveniently,” says Limor Fix, general chair of the 45th DAC. “This strategic collaboration reflects the overall trajectory of the semiconductor industry as manufacturers realize the necessity of considering test requirements during the design phase, and it reinforces DAC’s commitment to being the epicenter of electronic design.”
“In selecting the city and dates for GSC this year, we felt that our membership would be very interested in attending both conferences,” adds Keith Imai, GSC chairman. “This alliance will highlight the benefits of attending GSC and DAC for our combined attendee audiences.”
Call for Exhibitors:
DAC is actively expanding its exhibitor base to encompass the entire design eco-system from embedded software and system-level design tools, IP, EDA, and design services through to silicon manufacturing. The expanded scope of the show floor along with DAC's unique booth/suite combination and world-class conference and educational program makes participation a must for companies with products used in the design and development of circuits and systems.
Nominations for the Marie R. Pistilli Women in EDA Achievement Award Accepted Until March 7
DAC announced today that nominations are being accepted until March 7 for the Marie R. Pistilli Women in Electronic Design Automation (EDA) Achievement Award. Named for Marie R. Pistilli, the former organizer of DAC, the award, now in its ninth year, recognizes individuals who have contributed significantly to the advancement of women in the EDA industry. This year's award will be presented to the 2008 recipient at the Workshop for Women in Design Automation (WWINDA) on Monday, June 9, during the 45th DAC in Anaheim, Calif. Registration for WWINDA and DAC will open March 24.
“This annual award is an important way of acknowledging the significant contributions of women to this industry,” said Peggy Aycinena, this year's WWINDA chair: “We look forward to reviewing this year's nominations and learning more about the individuals who are advancing women in EDA.”
To be considered, an individual should have been responsible for the launch or management either of a successful product that included contributions from women, or a program that has created opportunities for women. Nominees may also be leaders within a company or organization that has helped raise the awareness of women, or they may have served as a mentor or role model for successful women in EDA.
The award is open to both men and women with technical or non-technical backgrounds in industry or academia. For more information on the award, including previous recipients and nomination forms, visit the DAC website.
The Absolute Need for Design and Test to be Closely Linked
The Semiconductor Test Consortium (STC) is very pleased to be a Conference Alliance Partner with DAC and congratulates the entire organization on its 45th anniversary. (See details under DAC news.) Our partnership is indicative of synergistic cooperation that is essential in today’s dynamic environment, where the need for design and test to be closely linked together has never been higher.
The industry’s ability to keep up with Moore’s Law has exponentially driven the design complexities of today’s ICs. Typical SoC designs integrate a wide variety and number of technologies including microprocessors, memories, digital, analog, mixed-signal and RF. The ability to test such highly integrated devices with an appropriate fault coverage and quality level, is a challenge; to efficiently do it at consumer-market pricing is a daunting task.
The days of throwing a design over the fence and having a test engineer successfully test it are long gone. The explosion of design tools, wafer fab, packaging and test technologies has necessitated the design for manufacturing (DFM) philosophy. Backend considerations such as test methodology and final die format (known good die, packaged die, SIP, etc.), must be contemplated and accounted for at the design phase.
On top of the technical challenges, there are also market dynamics to contend with. In recent years, the semiconductor industry has evolved from being enterprise-driven to consumer-driven. This drastic market shift has altered the supply chain dynamics, which start with IC design and end with test. The “hockey stick” ramp to production (if and when it happens for those “must have” products) creates a great strain on the entire supply chain to maximize efficiencies and profits quickly, while preparing for the next killer app due out next quarter. The overall effect is that the supply chain has become compressed, just like the IC lifecycles. This places a premium on the ability to routinely bring products to market quickly and efficiently.
By developing and adopting standardized hardware and software interfaces, such as STIL, the industry can better manage this dynamic environment. The STC has recently launched the Semiconductor Test Interface eXtensions (STIXTM) initiative, which focuses on standardizing the interfaces around Automatic Test Equipment (ATE), which is treated as a non-architecture specific “black box.” Standardized interfaces between the various supply chain segments enable innovative solutions, create economies of scale and shorten time-to-market/volume/profit.
As an example, the STC STIL Working Group endeavors to leverage the initial work done by the IEEE STIL group by industrializing their efforts to enable open tools to facilitate the interface between the design and test environments. Based on membership interest, other STC working groups are forming, including Yield Enhancement Analysis Tools, to address how to best handle the vast array of test data that is now necessary to efficiently run high production volumes, especially when managing multiple offshore locations.This year, STC will host or participate in 19 global events, tradeshows and meetings. Once a year, the Global STC Conference (GSC) is held to bring the worldwide membership and industry together. The next GSC will be June 4-6 in San Diego, Calif. Fittingly, this year’s theme is “Collaborative Solutions Beyond 2010.” One of the goals is to bring the design and test communities closer together to discuss the mutual challenges we face as an industry. Additional information.
About the Semiconductor Test ConsortiumThe STC was founded in 2003 and is the leading proponent of the development and adoption of value-added open test standards that benefit the semiconductor industry. Membership is open to all companies throughout the semiconductor supply chain with a vested interest in the test sector. More information can be found at www.semitest.org
The Pace Quickens, the Scope Widens
by Gabe Moretti
The frequency of publication of the DACeZine is increasing to twice a month beginning with this issue. We do so, beginning in March every year, to accommodate the increase in the number of articles needed to cover all of the relevant news surrounding the conference.
In this issue, the article by Geoffrey James continues our coverage of the discourse surrounding analog design tools and methods. Most observers of the EDA industry have identified this market segment as being ready for significant growth and increased competition, after years in which Cadence's Virtuoso has been the functionality and compatibility benchmark for every new analog design product. Just last week, Magma introduced the Titan platform, aimed at supporting analog and mixed/signal designs, and more products are rumored to be on the verge of public announcement, making the upcoming DAC conference the proper venue for attendees interested in new opportunities in analog, mixed-signal, and RF design solutions.
What is becoming a regular column for the DACeZine, the Round Table moderated by Ed Sperling, took place during DVCon. Participants—including yours truly—addressed the issue of the changing communication ecosystems in EDA. We discussed the respective roles of blogs, generic publications, as well as publications dedicated to covering only one aspect of the design flow or one specific application area. Of course, the discourse is only the beginning—one hour or so is not enough—and more contributions are welcome. Let me hear from you by your writing to me. But what seems to me important to point out here is that this publication, DACeZine, is at the forefront of the change in communication patterns. One of DACeZine’s most unique characteristics is that it offers to both exhibitors and attendees of DAC the best opportunity available anywhere to communicate, discuss, and learn. People that read it are, by definition, either past conferences' attendees, or individuals interested in both EDA and DAC as its premier annual event.
I am very happy to welcome the Viewpoint by Keith Imai, chairman of GSC, the Global Conference of the Semiconductor Test Consortium. GSC and DAC, as you can read in an article in this issue, have formed a conference alliance partnership that underscores the importance of test planning during design as well as the contributions of test strategies to the success of design teams. As the leading EDA conference, DAC is building strong relationships with other segments of the electronics industry because it realizes the importance of thinking globally, from architectural design to final test, in facilitating the financial success of the companies and professionals that make up our constituency.
I welcome suggestions, differing opinions, and even (gentle!) criticism. Let me hear from you by writing to me: address your content to email@example.com.
The DACeZine also has a Letters to the Editor section to allow for shorter contributions to the contents and directions of the publication. When necessary, answers to the letters will come from the appropriate member of the team (including our readers), since I do not (yet) hold the total knowledge of the industry within me. I encourage all of you to write, either a viewpoint or a letter, and state your opinions on matters that impact our industry, the contents of this publication, or, for that matter, the publication itself. Send your letters to: firstname.lastname@example.org.
Automatic Analog Design
Is it really a black art or just a red herring?
by Geoffrey James
For years, the EDA industry has been calling analog IC design a black art—tool makers wag their heads sadly at the difficulties of automating it. Many industry experts still espouse that view, but there are a growing number of voices saying that the challenge has been overrated and that the recalcitrance of the analog designer community might be as much of a problem as the inherent complexity of analog design itself. Is analog design truly a black art? And, if not, why do so many think it is? And when will the EDA industry see the breakthroughs that will automate analog IC design, thus transforming it from an art into a science?
State of the Black Art
Analog IC design also requires a deep understanding of physics and how components react to each other in the silicon environment. As a consequence, "the study of analog design is very hard…much harder than digital design," says Mike Demler, product marketing manager for Synopsys's analog simulation tool. Analog design requires expert knowledge of the fundamental principles of electronics, circuit theory, semiconductor physics, signal processing theory, advanced mathematics and so forth. As a result, "engineers who choose to pursue analog design as a career must study (and master) a large body of science," says Demler, "Those who can do that and then apply their knowledge creatively are scarce."
To make matters worse, analog design gets more difficult as the industry moves to ever-smaller nodes. "The physical effects of nanometer processes have introduced variability, the need to manage leakage and power while maintaining performance with lower supply voltages, and the requirement for analysis of numerous post-layout effects," says Demler. Furthermore, the complexity of design rules at 65 and 45nm and below makes it hard for human engineers to optimize an analog design (especially the physical layout) in an acceptable timeframe, according to Filseth.
Despite the complexity, though, it's probably an overstatement to call analog IC design a black art. "There are definitely parts of the custom analog design process that are sufficiently rote to be computerized," claims Steve Lewis, a director of product marketing at Cadence. "The trick is to concentrate on removing some of the drudgery from the process," he says. EDA pundit Gary Smith of Gary Smith EDA believes that at least some of the difficulties associated with automating analog design lie in a general unwillingness, among analog designers, to cooperate with EDA tool builders. "Analog engineers have been by far the highest paid of the two and analog IC vendors also have far better margins than the digital vendors," he says, "Keeping the perception of analog design as a black art has been in their best interests."
Analog Wagging the Digital Dog
A similar "de-skilling" process took place among digital IC designers, according to Chris Collins, director of analog technology infrastructure at Texas Instruments. "The best thing to ever happen to digital was when a voltage was quantized into a zero and a one," he explained, "Many great EDA tools were then developed around that sort of structure and it certainly made digital design into a commoditized trade...literally anyone could do it." As a result, digital IC designers now command significantly lower salaries than their analog brethren.
Unfortunately, "automating" something as complicated as analog design is only possible with the direct cooperation of the folk being "automated." And that's created a conflict of interest for EDA firms who haven't been willing to irritate the analog designers, lest they stop buying their tools. "If you annoy your constituency, they'll just say 'we won't do it," says Cadence's Lewis, "Most companies have a shortage of analog master designers and they're like the tip of the tail that wags the dog."
However, that dysfunctional dynamic is beginning to change as the result of two major trends, according to Gary Smith. The first trend is the aging of the workforce. "The good news is the old farts are retiring and the new analog guys are willing to use tools," he says. The second trend is the injection of foreign design firms into the mix. "Asia has come up as a major analog area and in Asia there is no separate analog/digital engineer categories; they are all just IC designers," says Smith. And that makes them more willing to cooperate when it comes to co-developing tools that might add more automation into the analog design process.
This is not to say that there's will be a change overnight. "It is in my opinion that analog design is still a guild art in many ways and the best analog designers are Master Craftsmen in their trade," says Collins, who believes that it may be a decade, or more, before the promise of analog automation can truly reach fruition. "The EDA industry is still very much today where it was in the late 80's when it comes to analog software innovation," he explains, "By and large, the analog EDA industry is still the 'netlist and simulate' EDA industry (which) continues to add to the mystique and black art persona of analog design."
Where Did You Hear That?
The ongoing breakdown in the advertising model leaves engineers and executives on their own for information gathering; expect to put in more hours sifting through data.
DACeZine sat down to discuss the future of information gathering with Limor Fix, principal engineer and associate lab director at Intel Research Pittsburgh and general chair, 45th DAC; J.L. Gray, consultant at Verilab who runs the Cool Verification Blog; David Maliniak, EDA editor at Electronic Design; and Gabe Moretti, managing editor of Gabe on EDA. What follows are excerpts of that conversation.
By Ed Sperling
Q: With the traditional business media collapsing around us, where will engineers and executives go to get their information?
Q: So where do engineers go, once the dust settles?
Q: Do you trust blogs more than professionally written stories?
Q: So what you’re looking for is triangulation of information?
Q: Is that something the press has done traditionally?
Q: Three years from now, where will you go for information and what will you expect to get?
Q: Who’s going to be writing those articles?
Q: But isn’t a broad-based publication comparable to a supermarket, where you no longer have to go cut deals with each fruit and vegetable vendor? Given what you’re talking about, you will have to work much harder to get your information, right?
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