Six hundred and eighty-two (682) regular papers were submitted (a seven percent jump from last year’s 639 papers) and 22% were accepted. Areas with highest submission numbers are:

• System-level design and codesign (87 papers were submitted; accepted papers will be presented in five sessions)
• Power analysis and low-power design (83 papers were submitted;
four sessions)
• Physical design and manufacturability (82 papers were submitted;
four sessions)
• High-level and logic synthesis (54 papers were submitted; three sessions)

In addition to regular paper sessions, DAC’s technical program consists of Special Sessions, Panels, Tutorials, Workshops, and Colocated Events. The introduction of the User Track, with its emphasis on design methodology and tool flows, is new this year. The User Track had 117 submissions, and the accepted papers will be presented in nine sessions (five for the front end, four for the back end) as well as in a new poster session on Wednesday afternoon.

Special Sessions will deal with a wide variety of themes such as preparing for design at 22nm, designing circuits in the face of uncertainty, verification of large, systems-on-chip, bug-tracking in complex designs, novel computation models, multicore computing and the impact of data centers on computing and EDA. The special sessions continue to include WACI (Wild and Crazy Ideas)—forward-looking and innovative ideas that are typically less developed than regular papers.
Technical Panels present the hottest issues of our industry and will cover:

• Technical discussions on system prototyping, embedded software design, mixed signal verification, system-level power challenges, design for manufacturability, emerging applications of EDA technology, and the previously-noted special plenary panel, “How Green is My Silicon Valley”.
• Management-focused topics such as costs of scaling, careers in EDA, and the return of the CEO panel.

The program also features six Full-day Tutorials on timely subjects ranging from parallel programming and its application to CAD tools, high-level synthesis, post-silicon validation, functional verification, low-power design in the wireless space, and the future of circuits based on emerging nanodevices.

Panels

System Prototypes: Virtual, Hardware or Hybrid?
Tuesday, July 28, 10:30am - 12:00pm
EDA in Flux—Should I Stay or Should I Go?
Tuesday, July 28, 2:00pm - 4:00pm
Moore’s Law: Another Casualty of the Financial Meltdown?
Tuesday, July 28, 4:30pm - 6:00pm
DFM—Band-Aid or Competitive Weapon?
Wednesday, July 29, 9:00am - 11:00am
Oil Fields, Hedge Funds and Drugs
Wednesday, July 29, 2:00pm - 4:00pm
Guess, Solder, Measure, Repeat—How Do I Get My Mixed-Signal Chip Right?
Wednesday, July 29, 4:30pm - 6:00pm
From Milliwatts to Megawatts: The System-Level Power Challenge
Thursday, July 30, 2:00pm - 4:00pm
The Wild West: Conquest of Complex Hardware-Dependent Software Design
Thursday, July 30, 4:30pm - 6:00pm

Special Sessions

Mechanisms for Surviving Uncertainty: Opportunities and Prospects
Tuesday, July 28, 10:30am - 12:00pm
Dawn of the 22nm Design Era—Yes We Can!
Tuesday, July 28, 2:00pm - 4:00pm
Verifying an SOC Monster: Whose Job Is It Anyway?
Tuesday, July 28, 4:30pm - 6:00pm
Emerging Technologies: Blue-Sky Research or CMOS Replacement?
Wednesday, July 29, 9:00am - 11:00am
Computation in the Post-Turing Era
Wednesday, July 29, 2:00pm - 4:00pm
Multicore Computing and EDA
Wednesday, July 29, 4:30pm - 6:00pm
WACI: Wild and Crazy Ideas
Thursday, July 30, 9:00am - 11:00am
The Tool Shows That My Design Is Wrong, But Where Is the Bug?
Thursday, July 30, 9:00am - 11:00am
Technologies for Green Data Centers
Thursday, July 30, 4:30pm - 6:00pm