Challenges and Opportunities Keep the Industry Going
This is a double issue, covering both November and December and offering nine articles, including this one. Before I get to the business side of things, I would like to take this opportunity to wish Happy Holidays to all of our readers.
The industry is facing hurdles, many not entirely of its own doing and, for some, the immediate future seems discouraging. But EDA has overcome challenges before. Our professional members are creative and cherish challenges. I cannot predict when, but I know we will come out of this trial as a better and stronger industry.
DAC is once again at the forefront in responding to new conditions and requirements by introducing a new track to its program. The User Track will provide designers and EDA developers with the opportunity to network and exchange experiences regarding methods and tools presently used. Other tracks in the program will continue to look forward and push the envelope of future technical possibilities. The article in this issue, "The User Track: It's All About You!," as well as the one on the same subject published in the October issue will give you all the details about this new initiative.
We are not stopping here. Submissions to the technical program, panels, DAC pavilion panels and other activities are coming in, and it looks like the 46th DAC that will be held July 26-31 in San Francisco will be a must-attend event.
Physical Design is the main topic of this issue. The topic covers all aspects of design required to transform a RTL netlist into data used to actually manufacture a device. Much has been said about Design for Manufacturing (DFM), an important component of such a flow. I think more must be said about Manufacture for Designability (MFD). This issue offers a technical article that provides a start to discuss such topic (... which I just created).
Joe Sawicki, vice president and general manager of Mentor's Design-to-Silicon division, has contributed an article that looks at the latest challenges facing designers in implementing their designs in silicon. The title, "Connecting IC design and fabrication to reduce manufacturing variability," clearly describes the contents.
The landscape of EDA vendors that support physical design (Tools and services for physical design of ICs), generated as usual by the intersection of the 45th DAC exhibitors and the contents of Gary Smith Wallchart, contains the largest number of vendors so far.
We all know that design complexity has required many methodology changes. One of the most striking is the increased dependency among tasks that were once considered sequential. Lauro Rizzatti, of EVE-USA points this out in his Viewpoint titled, "And Now, the Hard Part: Verification."
The DAC Vice Chair is a key member of the DAC Executive Committee. Peggy Aycinena's interview of Sachin Sapatnekar, who is the 46th DAC vice chair and finance chair, provides not only a profile of the person, but also a view at the thinking that will shape DAC in the future. Find the full article titled, "DACeZine Profile: Sachin Sapatnekar."
We also have news about the conference: a call for papers for the Student design contest and a notice of an award named after Richard Newton, a key contributor to the growth of EDA. Nominations are now open for this award that is sponsored by ACM SIGDA and IEEE CEDA.
Finally, don't miss "DAC Planning Under Way" for a look at what it takes to deliver a successful conference.