Member Rates: $175
Non-Member Rates: $225

The NEW DAC User Track


sponsored by Cadence
User Track Invitation from Soha Hassoun

This new designer-oriented program showcases real-world experiences in the design of complex chips using CAD tools from multiple vendors. Topics covered range from system design exploration and embedded software synthesis in the front end, to constraint generation and physical verification in the back end.

You'll hear the full details without the marketing spin, in 40 exciting technical presentations by users of EDA tools. Speakers includeexpert designers from virtually all major companies, including Intel, Samsung, Qualcomm, and many others. A poster session on Wednesday, July 29 provides 40 additional presentations.

The User Track is a unique opportunity to discover how EDA tools from various vendors are being used at the leading edge of practice. You'll be able to update your knowledge base with best practices in EDA tools, while exchanging experiences with fellow designers.

USER TRACK: Robust Design and Test
TUESDAY - July 28, 10:30am - 12:00pm / Room: 132
USER TRACK: Practical Physical Design
TUESDAY - July 28, 2:00pm - 4:00pm / Room: 132
USER TRACK: Verification: A Front-End Perspective
TUESDAY - July 28, 4:30pm - 6:00pm / Room: 132
USER TRACK: Timing Analysis in the Real World
WEDNESDAY - July 29, 9:00am - 11:00am / Room: 132
USER TRACK: Poster Session and Ice Cream Social
WEDNESDAY - July 29, 1:30pm - 3:00pm / Concourse Level
USER TRACK: Toward Front-End Design Productivity
WEDNESDAY - July 29, 3:00pm - 4:00pm / Room: 132
USER TRACK: Front-End Development: Embedded Software and Design Exploration
WEDNESDAY - July 29, 4:30pm - 6:00pm / Room: 132
USER TRACK: Power Analysis and IP Reuse
THURSDAY - July 30, 9:00am - 11:00am / Room: 132
USER TRACK: Front-End Power Planning and Analysis
THURSDAY - July 30, 2:00pm - 4:00pm / Room: 132
USER TRACK: Advances in Analog and Mixed-Signal Design
THURSDAY - July 30, 4:30pm - 6:00pm / Room: 132