The DAC User Track, now in its second year, focuses on significant contributions from the EDA tool user community. In contrast to the traditional focus at DAC on algorithmic and methodology contributions, this track aims to share challenges and benefits of tool usage and provides educational and networking benefits for end users as well as tool developers. The User Track differs from vendor-specific user forums in that it is not tied to a specific EDA vendor.
The DAC 2010 User Track seeks submissions that highlight the challenges and benefits of EDA tool usage. The tools used may be from EDA vendors, developed in-house, or the result of combining one or more point tools. We specifically seek contributions from EDA users, application engineers, or a vendor-customer team. The tool use may target chip design at all levels of abstraction, and across all application domains.
At its core, a suitable User Track presentation describes a flow for combining and applying point-tool design, optimization, and analysis, to build blocks that achieve particular design goals. A submission may be specific in scope (e.g., floorplan-stage substrate coupling) and in application domain (e.g., designing wireless handsets).Submissions may also present an investigative case study (e.g. potential use of a tool to accomplish a goal).
User Track Submission Categories
Authors are required to specify a category from the following list that reflects the type of tools that were used or the methodology most relevant to the submission:
1. System-Level Design (Front-End):
1.1. Hardware/Software Co-Design
1.2. System and High-Level Hardware Synthesis
1.3. Power/Area/Performance Trade-Offs
1.4. Embedded Software Tools
1.5. Bus and Network Communication Strategies
1.6. Emulation and Verification
1.7. IP Blocks and Integration
2. Silicon-Level Design (Back-End):
2.1. Physical Synthesis Tools and Techniques
2.2. Floorplanning
2.3. Timing and Circuit Analysis
2.4. DRC and DFM
2.5. Test and Debug
2.6. Analog and Mixed-Signal Design
2.7. Custom, Standard Cell and FPGA Design Flows
2.8. Packaging and Board Integration