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 | WEDNESDAY, June 15, 2005, 02:00 PM - 05:00 PM | Room: 211AB TRACK:SYSTEM-LEVEL DESIGN AND VERIFICATION | |
| HoT Core-based SoC Design | ||
| Using Configurable Processors to Replace RTL Blocks (Tensilica, Inc. and Virage Logic Corp.) | ||
 Configurable processors can be tailored to an exact application and are often used to replace blocks of RTL. Because configurable processors employ firmware instead of RTL-defined state machines for their control algorithms, it's easier and faster to develop and verify processor-based task engines for many embedded SoC tasks than to develop and verify RTL-based hardware to perform the same tasks. Tensilica lets designers add specialized functions right into the processor's execution units without requiring that the designers understand the processor architecture. Configurable processors are delivered as synthesizable RTL code, ready for placement into an FPGA or SoC design.
This 3-hour tutorial will show how to design a configurable processor with the equivalent performance to hand-coded RTL using Tensilica's XPRES compiler, which automatically analyzes C code to determine the best processor configuration and extensions. This tutorial will also show how to evaluate and select the optimal embedded memory IP for their Xtensa processor configurations using a web-based portal interface from Virage Logic. This tutorial will show the performance impact of various different memory configurations, and how important it is to tightly match the memory to the processor configuration. | ||