The design of such multi-core systems requires novel integrated EDA flows, addressing both the design of new ASIP cores, the delivery of software development tools for such cores, and a seamless integration of all cores in a system-level model based on SystemC. The purpose of this hands-on tutorial is to introduce such a design flow, based on offerings from EDA vendors Mentor and Target.

The key tools that will be combined in this tutorial are:

ˇMentor's ModelSim environment, one of the industry's most complete multi-level simulation tools, from SystemC up to RTL level.
ˇTarget's Chess/Checkers environment, a state-of-the-art retargetable tool-suite for the design, programming and verification of ASIPs.

The tutorial will demonstrate how new ASIP cores can be designed and programmed quickly, while at the same time ensuring the correctness of the design, not only at the level of individual cores but also at the overall system level.

In the hands-on exercises, participants will design a small demo application, including the following steps:

ˇHigh-level SystemC simulation of the overall application, using ModelSim.
ˇDesign and programming of a few ASIP cores for some key functions of the system, using the Chess/Checkers tools. This will include C compilation onto these ASIP cores, as well as the automatic generation of a cycle accurate instruction-set simulator (ISS) and of a synthesizable Verilog model of each core.
ˇVerification of the architecture design, by integrating the generated ISSs in System C and running co-simulation in ModelSim.
ˇVerification of the hardware, by integrating the generated Verilog models of the ASIP cores in an RTL netlist of the total system, and simulating everything in ModelSim.

A basic knowledge of SystemC, Verilog, and processor architecture would be recommended for participating in this tutorial.