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 | MONDAY, June 13, 2005, 09:00 AM - 05:00 PM | Room: 210AB TRACK:DESIGN FOR MANUFACTURING | |
| MONDAY TUTORIAL | ||
| #1 - Statistical Performance Analysis and Optimization of Digital Circuits | ||
| Organizer(s): Ruchir Puri | ||
 On-chip variations have become an increasing concern in integrated circuits as circuit sizes continue to increase and feature sizes continue to shrink. As device and interconnect parameters such as physical dimensions show variability, the prediction of circuit performance, both in terms of delay and power, has become a challenging task. Conventional approaches that handle the problem of variability using multiple process corners must be replaced by a statistical paradigm that incorporates the complexities of intra-die variations, inter-die variations, deterministic variations, random variations, or related variations, etc.
This tutorial will present a comprehensive overview of methods that are required to move to a truly statistically-based performance framework, focusing on designs with high timing and power yield. The presentation is directed towards researchers and practitioners in industry working on cutting-edge nanometer-scale designs. It will consist of several parts that cover issues from fabrication to design to CAD: roughly speaking, the segments will deal with the extraction of fab information into distributions for analysis; circuit structures and techniques to reduce on-chip variability; and CAD for the analysis and optimization of timing and power. | ||
| Speaker(s): | Sachin Sapatnakar - Univ. of Minnesota, Minneapolis, MN Vivek De - Intel Corp., Portland, OR Michael Orshansky - Univ. of Texas, Austin, TX Nagib Hakim - Intel Corp., Santa Clara, CA |
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