Attend this hands-on tutorial to experience a design flow that uses CoWare's System Level Design to explore and extend the functionality of a MIPS32® 24K™ Pro Microprocessor core while achieving fast turnaround and low cost re-spin design using Virage Logic's ASAP Logic Metal Programmable library with Magma's unified implementation flow. In this tutorial, attendees will observe a complete system level design process, starting from exploring the system architecture, trading-off hardware and system software partitioning and the creation of CorExtend User Defined Instructions using CoWare's CorXpert. The resultant Instructions can then be synthesized in the RTL implementation flow. The CorExtend block serves to extend the instruction set of the MIPS core so that the hardware can better perform application-specific tasks. CorExtend instructions also provide flexibility to extend the capability of the base design with faster design turn around time and lower manufacturing cost.
Two methods on how to implement the CorExtend block will be shown:
1. Synthesize the entire core and the extended block together using metal programmable library.
2. Synthesize only the extended block using metal programmable library.
In the first implementation, we will demonstrate the entire implementation of the MIPS core using Virage Logic's ASAP Logic Metal Programmable cell library to achieve a near standard cell-like performance, including the enhanced CorExtend block to provide greater flexibility to optimize the design for a specific application. Secondly, we will isolate a CorExtend block using the metal programmable cell library and implement the core logic with the ASAP Logic High-Density standard cell library from Virage for performance optimization.
Both approaches take advantage of MIPS inherent high-performance architecture, Magma's unified flow to achieve the best quality of results and Virage Logic's Metal Programmable Cell Library to reduce design cycles and lower manufacturing costs.
CoWare Hardware/Software Design Flow
CoWare's CorXpert design tool allows the rapid creation and exploration of the MIPS CorExtend Instructions, allowing system simulation and providing RTL synthesis, enabling the user to optimize the MIPS processor for their application software.
MIPS Technologies High-performance, Low-power Extendable Core
MIPS Technologies' 24K Pro family delivers the highest performance licensable 32-bit core in the market today. The 24K Pro Series™ cores with CorExtend offer unprecedented value by enabling SOC designers to write their own instruction set extensions and create highly differentiated, highly competitive products. The 24K's industry-leading performance consumes the lowest power of any comparable licensable core and is implemented in the smallest area, reducing total system costs.
The 24K core family is designed to power through graphics, Java and demanding applications with features like an ultrafast multiply, floating point support and the CorExtend capability. The 24K family is the ideal solution for digital and interactive television, set-top boxes, DVD and other performance-driven applications.
Magma Unified Implementation Design Flow
Magma unified flow takes advantages of the unified data model to streamline the design process from RTL to GDSII while concurrently optimize the design from various aspects. This reduces iteration while performs optimizations along the design process with the updated and real time design data feedback from the data model.
About Virage Logic's ASAP Logic Cell Libraries
The ASAP Logic Metal Programmable Cell Libraries significantly reduce overall mask costs by allowing minimum changes in masks to achieve any necessary product revisions or personalization of the chip. Performance and area are competitive with standard cell products currently in the marketplace.
This tutorial will cover the following topics:
1. CoWare CorXpert to capture and rapidly explore of the User Defined Instruction alternatives, to get the optimal performing CorExtend block for their application
2. MIPS Technologies MIPS32 24K Pro with CorExtend to add instructions for hardware/software tradeoffs
3. Magma unified flow to shorten the design cycle while achieving superior QoR.
4. Virage Logic ASAP Metal Programmable Library to speed up design turnaround time and reduce manufacturing cost.
Attend this hands-on tutorial to experience a design flow that uses CoWare's System Level Design to explore and extend the functionality of a MIPS32® 24K™ Pro Microprocessor core while achieving fast turnaround and low cost re-spin design using Virage Logic's ASAP Logic Metal Programmable library with Magma's unified implementation flow. In this tutorial, attendees will observe a complete system level design process, starting from exploring the system architecture, trading-off hardware and system software partitioning and the creation of CorExtend User Defined Instructions using CoWare's CorXpert. The resultant Instructions can then be synthesized in the RTL implementation flow. The CorExtend block serves to extend the instruction set of the MIPS core so that the hardware can better perform application-specific tasks. CorExtend instructions also provide flexibility to extend the capability of the base design with faster design turn around time and lower manufacturing cost.