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| TUESDAY, June 14, 2005, 4:30 PM - 6:30 PM | Room: 210CD | ||
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TOPIC AREA: NANOMETER ANALYSIS AND SIMULATION (tools) | ||
| SESSION 12 | |||
| Recent Advances in Signal Integrity | |||
| Chair: Eli Chiprout - Intel Corp., Chandler, AZ | |||
| Organizers: Dusan Petranovic, Lei He | |||
| This session describes advances in a range of topics in the signal integrity area. The first paper discusses an efficient approach to budgeting decoupling capacitance in order to improve power grid integrity. The next two papers discuss clock network optimization using register placement and a novel opposite-phase scheme to reduce peak current demands, respectively. The next paper details an effective capacitance model for fast noise analysis. The final paper presents an approach to selectively inserting hardened flip-flops in a general circuit to improve robustness while maintaining timing/area constraints. | |||
 12.1 |
Partitioning-Based Approach to Fast On-Chip Decap Budgeting and Minimization |
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| Speaker(s): | Hang Li - Univ. of California, Riverside, CA | ||
| Author(s): | Hang Li - Univ. of California, Riverside, CA Zhenyu Qi - Univ. of California, Riverside, CA Sheldon Tan - Univ. of California, Riverside, CA | ||
| 12.2 | Navigating Registers in Placement for Clock Network Minimization | ||
| Speaker(s): | Yongqiang Lu - Tsinghua Univ., Beijing, China | ||
| Author(s): | Yongqiang Lu - Tsing-Hua Univ., Beijing, China C. N. Sze - Texas A&M Univ., College Station, TX Xianlong Hong - Tsing-Hua Univ., Beijing, China Qiang Zhou - Tsing-Hua Univ., Beijing, China Yici Cai - Tsing-Hua Univ., Beijing, China Liang Huang - Tsing-Hua Univ., Beijing, China Jiang Hu - Texas A&M Univ., College Station, TX | ||
| 12.3s | Minimizing Peak Current via Opposite-Phase Clock Tree | ||
| Speaker(s): | Shih-Hsu Huang - Chung Yuan Christian Univ., Chung Li, Taiwan | ||
| Author(s): | Yow-Tyng Nieh - Chung Yuan Christian Univ., Chung Li, Taiwan Shih-Hsu Huang - Chung Yuan Christian Univ., Chung Li, Taiwan Sheng-Yu Hsu - Industrial Technology Research Institute, Hsin Chu, Taiwan | ||
| 12.4s | A Noise-Driven Effective Capacitance Method With Fast Embedded Noise Rule Calculation for Functional Noise Analysis | ||
| Speaker(s): | Haihua Su - IBM Corp., Austin, TX | ||
| Author(s): | Haihua Su - IBM Corp., Austin, TX David J. Widiger - IBM Corp., Austin, TX Chandramouli V. Kashyap - IBM Corp., Austin, TX Frank Y. Liu - IBM Corp., Austin, TX Byron Krauter - IBM Corp., Austin, TX | ||
| 12.5 | Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in Digital VLSI Circuits | ||
| Speaker(s): | Chong Zhao - Univ. of California at San Diego, La Jolla, CA | ||
| Author(s): | Chong Zhao - Univ. of California at San Diego, La Jolla, CA Yi Zhao - Univ. of California at San Diego, La Jolla, CA Sujit Dey - Univ. of California at San Diego, La Jolla, CA | ||
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