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| TUESDAY, June 14, 2005, 4:30 PM - 6:30 PM | Room: 210AB | ||
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TOPIC AREA: SYSTEM-LEVEL DESIGN AND VERIFICATION (mixed tools and methods) | ||
| SESSION 13 | |||
| Physical Considerations in High-Level Synthesis | |||
| Chair: Steven M. Burns - Intel Corp., Portland, OR | |||
| Organizers: Gila Kamhi, Reinaldo Bergamaschi | |||
| This session brings together five interesting papers using physical considerations (floorplanning and layout) in high-level synthesis. The first two papers deal with temperature and power issues in high-level design; the third paper considers floorplanning together with high-level synthesis for area and power optimization; the fourth paper deals with encoding techniques for power reduction; and the fifth paper uses specific layout techniques for watermarking. | |||
 13.1 |
Temperature-Aware Resource Allocation and Binding in High-Level Synthesis |
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| Speaker(s): | Rajarshi Mukherjee - Northwestern Univ., Evanston, IL | ||
| Author(s): | Rajarshi Mukherjee - Northwestern Univ., Evanston, IL Seda Ogrenci Memik - Northwestern Univ., Evanston, IL Gokhan Memik - Northwestern Univ., Evanston, IL | ||
| 13.2 | Leakage Power Optimization with Dual-Vth Library in High-Level Synthesis | ||
| Speaker(s): | Hai Zhou - Northwestern Univ., Evanston, IL | ||
| Author(s): | Xiaoyong Tang - Magma Design Automation, Inc., Santa Clara, CA Hai Zhou - Northwestern Univ., Evanston, IL Prith Banerjee - Univ. of Illinois, Chicago, IL | ||
| 13.3 | Incremental Exploration of the Combined Physical and Behavioral Design Space | ||
| Speaker(s): | Zhenyu Gu - Northwestern Univ., Evanston, IL | ||
| Author(s): | Zhenyu Gu - Northwestern Univ., Evanston, IL Jia Wang - Northwestern Univ., Evanston, IL Robert P. Dick - Northwestern Univ., Evanston, IL Hai Zhou - Northwestern Univ., Evanston, IL | ||
| 13.4s | Sign Bit Reduction Encoding For Low Power Applications | ||
| Speaker(s): | Zainolabedin Navabi - Univ. of Tehran, Tehran, Iran | ||
| Author(s): | Mohsen Saneei - Univ. of Tehran, Tehran, Iran Ali Afzali-Kusha - Univ. of Tehran, Tehran, Iran Zainolabedin Navabi - Univ. of Tehran, Tehran, Iran | ||
| 13.5s | A Watermarking System for IP Protection by a Post-Layout Incremental Router | ||
| Speaker(s): | Tingyuan Nie - Kochi Univ., Kochi, Japan | ||
| Author(s): | Tingyuan Nie - Kochi Univ., Kochi, Japan Tomowo Kisaka - Kochi Univ., Kochi, Japan Masahiko Toyonaga - Kochi Univ., Kochi, Japan | ||
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