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| TUESDAY, June 14, 2005, 10:30 AM - 12:00 PM | Room: 210CD | ||
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TOPIC AREA: LOGIC DESIGN AND TEST (methods) | ||
| SESSION 2 | |||
| Special Session: Error-Tolerant Design | |||
| Chair: Sarma Vrudhula - Univ. of Arizona, Tucson, AZ | |||
| Organizers: Krishnendu Chakrabarty, Sarma Vrudhula | |||
| Industry presentations on various aspects of soft errors - causes, impacts, and mitigation. Highlight conclusions of upcoming workshop on soft errors. | |||
 2.1 |
Logic Soft Errors in sub-65 nm Technologies: Design and CAD Challenges |
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| Speaker(s): | Subhasish Mitra - Intel Corp., Folsom, CA | ||
| Author(s): | Subhasish Mitra - Intel Corp., Folsom, CA Tanay Karnik - Intel Corp., Hillsboro, OR Norbert Seifert - Intel Corp., Hillsboro, OR Ming Zhang - Intel Corp., Folsom, CA | ||
| 2.2 | SEU-Tolerant Device, Circuit and Processor Design | ||
| Speaker(s): | Bill Heidergott - General Dynamics Decision Systems, Scottsdale, AZ | ||
| Author(s): | Bill Heidergott - General Dynamics Decision Systems, Scottsdale, AZ | ||
| 2.3 | System Effects of Transient Particle Induced Upsets | ||
| Speaker(s): | Pia N. Sanda - IBM Corp., White Plains, NY | ||
| Author(s): | Pia N. Sanda - IBM Corp., White Plains, NY Ethan H. Cannon - IBM Corp., VT Scott Swaney - IBM Corp., White Plains, NY David M. Cole - IBM Corp., White Plains, NY | ||
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