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WEDNESDAY, June 15, 2005, 10:30 AM - 12:00 PM | Room: 208AB
TOPIC AREA:  NANOMETER ANALYSIS AND SIMULATION (mixed tools and methods)

   SESSION 25
  Generating Efficient Models for Analog Circuits
  Chair: Richard Shi - Univ. of Washington, Seattle, WA
  Organizers: Koen Lampaert, Sandeep Shukla

  This session describes various techniques for generating efficient models for analog circuits. The first paper uses a novel operator-based model-order reduction algorithm to reduce a large linear periodically time-varying system into a smaller one. The second paper analyzes input and clock jitter effects in track and hold circuits. The last paper presents a scalable trajectory-based modeling methodology for generating on-demand macromodels for analog circuits.

    25.1   Operator-based Model-Order Reduction of Linear Periodically Time-Varying Systems
  Speaker(s): Yayun Wan - Univ. of Minnesota, Minneapolis, MN
  Author(s): Yayun Wan - Univ. of Minnesota, Minneapolis, MN
Jaijeet Roychowdhury - Univ. of Minnesota, Minneapolis, MN
    25.2Simulation of the Effects of Timing Jitter in Track-and-Hold and Sample-and-Hold Circuits
  Speaker(s): Vinita Vasudevan - Indian Institute of Tech., Madras, Chennai, India
  Author(s): Vinita Vasudevan - Indian Institute of Tech., Madras, Chennai, India
    25.3Scalable Trajectory Methods for On-Demand Analog Macromodel Extraction
  Speaker(s): Saurabh K. Tiwary - Carnegie Mellon Univ., Pittsburgh, PA
  Author(s): Saurabh K. Tiwary - Carnegie Mellon Univ., Pittsburgh, PA
Rob A. Rutenbar - Carnegie Mellon Univ., Pittsburgh, PA