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| WEDNESDAY, June 15, 2005, 2:00 PM - 4:00 PM | Room: 210CD | ||
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TOPIC AREA: LOGIC DESIGN AND TEST (tools) | ||
| SESSION 27 | |||
| CAD for FPGAs | |||
| Chair: Steve Trimberger - Xilinx, San Jose, CA | |||
| Organizers: Patrick Lysaght, Steven Teig, Steve Trimberger | |||
| FPGAs are rapidly rising in importance and pose a unique set of CAD challenges. This session presents a diverse collection of new techniques from both academic and industrial researchers. | |||
 27.1 |
Multiplexer Restructuring for FPGA Implementation Cost Reduction |
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| Speaker(s): | Paul Metzgen - Altera Corp., San Jose, CA | ||
| Author(s): | Paul Metzgen - Altera Corp., San Jose, CA Dominic Nancekievill - Altera Corp., San Jose, CA | ||
| 27.2 | FPGA Technology Mapping: A Study of Optimality | ||
| Speaker(s): | Andrew C. Ling - Univ. of Toronto, Toronto, Canada | ||
| Author(s): | Andrew C. Ling - Univ. of Toronto, Toronto, Canada Deshanand P. Singh - Altera Corp., Toronto, Canada Stephen D. Brown - Altera Corp., Toronto, Canada | ||
| 27.3 | Incremental Retiming for FPGA Physical Synthesis | ||
| Speaker(s): | Deshanand P. Singh - Altera Corp., Toronto, Canada | ||
| Author(s): | Deshanand P. Singh - Altera Corp., Toronto, Canada Valavan Manohararajah - Altera Corp., Toronto, Canada Stephen D. Brown - Altera Corp., Toronto, Canada | ||
| 27.4 | Architecture-Adaptive Range Limit Windowing for Simulated Annealing FPGA Placement | ||
| Speaker(s): | Ken Eguro - Univ. of Washington, Seattle, WA | ||
| Author(s): | Ken Eguro - Univ. of Washington, Seattle, WA Akshay Sharma - Univ. of Washington, Seattle , WA Scott Hauck - Univ. of Washington, Seattle, WA | ||
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