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WEDNESDAY, June 15, 2005, 2:00 PM - 4:00 PM | Room: 208AB
TOPIC AREA:  PHYSICAL CIRCUIT DESIGN (tools)

   SESSION 30
  Coping with Buffering
  Chair: Dinesh Gaitonde - Synopsys, Inc., Mountain View, CA
  Organizers: Dirk Stroobandt, Igor Markov

  This session introduces novel methods for economical buffer insertion. The first paper presents dual-Vdd buffer tree construction for power minimization under delay constraints. The next two papers focus on minimizing the overall number of repeaters in a circuit. The fourth paper resolves overlaps between repeaters and pre-existing cells.

    30.1   Power Optimal Dual-Vdd Buffered Tree Considering Buffer Stations and Blockages
  Speaker(s): King Ho Tam - Univ. of California, Los Angeles, CA
  Author(s): King Ho Tam - Univ. of California, Los Angeles, CA
Lei He - Univ. of California, Los Angeles, CA
    30.2Net Weighting to Reduce Repeater Counts During Placement
  Speaker(s): Brent Goplen - Univ. of Minnesota, Minneapolis, MN
  Author(s): Brent Goplen - Univ. of Minnesota, Minneapolis, MN
Prashant Saxena - Synopsys, Inc., Hillsboro, OR
Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN
    30.3Path Based Buffer Insertion
  Speaker(s): Cliff C.N. Sze - Texas A&M Univ., College Station, TX
  Author(s): Cliff C.N. Sze - Texas A&M Univ., College Station, TX
Charles J. Alpert - IBM Corp., Austin, TX
Jiang Hu - Texas A&M Univ., College Station, TX
Weiping Shi - Texas A&M Univ., College Station, TX
    30.4Diffusion-Based Placement Migration
  Speaker(s): Haoxing Ren - IBM Corp. & Univ. of Texas, Austin, TX
  Author(s): Haoxing Ren - IBM Corp. & Univ. of Texas, Austin, TX
David Z. Pan - Univ. of Texas, Austin, TX
Charles J. Alpert - IBM Corp., Austin, TX
Paul Villarrubia - IBM Corp., Austin, TX