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WEDNESDAY, June 15, 2005, 4:30 PM - 6:30 PM | Room: 210CD
TOPIC AREA:  DESIGN FOR MANUFACTURING (mixed tools and methods)

   SESSION 32
  Impact of Process Variations on Power
  Chair: Sunil Khatri - Texas A&M Univ., College Station, TX
  Organizers: Naehyuck Chang, Chaitali Chakrabarti

  In this session, there are four papers that examine the impact of process variations on power. The first paper computes the full chip leakage power under process variations considering intra-die, inter-die variations and spatial correlations. The second paper examines a design of a low-power parallel system based on voltage scaling considering within-die variations and temperature fluctuations. The correlation between delay and power is the subject of the third paper. Finally, the fourth paper presents a convex optimization procedure to find the exact minimum leakage considering process variations.

    32.1   Full-Chip Analysis of Leakage Power Under Process Variations, Including Spatial Correlations
  Speaker(s): Hongliang Chang - Univ. of Minnesota, Minneapolis, MN
  Author(s): Hongliang Chang - Univ. of Minnesota, Minneapolis, MN
Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN
    32.2Variations-Aware Low-Power Design with Voltage Scaling
  Speaker(s): Navid Azizi - Univ. of Toronto, Toronto, Canada
  Author(s): Navid Azizi - Univ. of Toronto, Toronto, Canada
Muhammad M. Khellah - Intel Corp., Hillsboro, OR
Vivek De - Intel Corp., Hillsboro, OR
Farid N. Najm - Univ. of Toronto, Toronto, Canada
    32.3Accurate and Efficient Parametric Yield Estimation Considering Correlated Variations in Leakage Power and Performance
  Speaker(s): Ashish Srivastava - Univ. of Michigan, Ann Arbor, MI
  Author(s): Ashish Srivastava - Univ. of Michigan, Ann Arbor, MI
Saumil S. Shah - Univ. of Michigan, Ann Arbor, MI
Kanak B. Agarwal - Univ. of Michigan, Ann Arbor, MI
Dennis M. Sylvester - Univ. of Michigan, Ann Arbor, MI
David Blaauw - Univ. of Michigan, Ann Arbor, MI
Stephen Director - Univ. of Michigan, Ann Arbor, MI
    32.4Leakage Minimization of Nano-scale Circuits in the Presence of Systematic and Random Variations
  Speaker(s): Sarvesh Bhardwaj - Arizona State Univ., Tempe, AZ
  Author(s): Sarvesh Bhardwaj - Arizona State Univ., Tempe, AZ
Sarma B. Vrudhula - Arizona State Univ., Tempe, AZ