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| WEDNESDAY, June 15, 2005, 4:30 PM - 6:30 PM | Room: 208AB | ||
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TOPIC AREA: PHYSICAL CIRCUIT DESIGN (tools) | ||
| SESSION 35 | |||
| New Approaches to Physical Design Problems | |||
| Chair: Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA | |||
| Organizers: Louis Scheffer, Malgorzata Marek-Sadowska | |||
| Traditional physical design problems are attacked by new methods and algorithms. This includes a floorplanner that considers micro-architecture, two new core placement algorithms, and an implementation of the recent X routing ideas. | |||
 35.1 |
Microarchitecture-Aware Floorplanning Using a Statistical Design of Experiments Approach |
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| Speaker(s): | Vidyasagar Nookala - Univ. of Minnesota, Minneapolis, MN | ||
| Author(s): | Vidyasagar Nookala - Univ. of Minnesota, Minneapolis, MN Ying Chen - Univ. of Minnesota, Minneapolis, MN David Lilja - Univ. of Minnesota, Minneapolis, MN Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN | ||
| 35.2 | Timing-Driven Placement by Grid-Warping | ||
| Speaker(s): | Zhong Xiu - Carnegie Mellon Univ., Pittsburgh, PA | ||
| Author(s): | Zhong Xiu - Carnegie Mellon Univ., Pittsburgh, PA Rob A. Rutenbar - Carnegie Mellon Univ., Pittsburgh, PA | ||
| 35.3 | Faster and Better Global Placement by a New Transportation Algorithm | ||
| Speaker(s): | Ulrich Brenner - Universität Bonn, Bonn, Germany | ||
| Author(s): | Ulrich Brenner - Universität Bonn, Bonn, Germany Markus Struzyna - Universität Bonn, Bonn, Germany | ||
| 35.4 | Multilevel Full-Chip Routing for the X-Based Architecture | ||
| Speaker(s): | Tsung-Yi Ho - National Taiwan Univ., Taipei, Taiwan | ||
| Author(s): | Tsung-Yi Ho - National Taiwan Univ., Goleta, CA Chen-Feng Chang - National Taiwan Univ., Taipei, Taiwan Yao-Wen Chang - National Taiwan Univ., Taipei, Taiwan Sao-Jie Chen - National Taiwan Univ., Taipei, Taiwan | ||
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