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TUESDAY, June 14, 2005, 10:30 AM - 12:00 PM | Room: 209AB
TOPIC AREA:  POWER (tools)

   SESSION 4
  Leakage Analysis and Optimization
  Chair: Yu Cao - Arizona State University, Tempe, AZ
  Organizers: Tanay Karnik, Chandu Visweswariah

  This session presents several different techniques for leakage analysis and optimization. The first paper presents a technique for total power reduction using gate sizing and multiple VT. The second paper describes a technique for reducing the short-circuit current when MTCMOS circuits transition from sleep to active state. The third paper dynamically determines the optimal reverse body bias for leakage control. The last paper shows a new technique of gate replacement for leakage reduction.

    4.1   Total Power Reduction in CMOS Circuits via Gate Sizing and Multiple Threshold Voltages
  Speaker(s): Feng Gao - Univ. of Michigan, Ann Arbor, MI
  Author(s): Feng Gao - Univ. of Michigan, Ann Arbor, MI
John P. Hayes - Univ. of Michigan, Ann Arbor, MI
    4.2An Effective Power Mode Transition Technique in MTCMOS Circuits
  Speaker(s): Afshin Abdollahi - Univ. of Southern California, Los Angeles, CA
  Author(s): Afshin Abdollahi - Univ. of Southern California, Los Angeles, CA
Farzan Fallah - Fujitsu Labs of America, Inc., Sunnyvale, CA
Massoud Pedram - Univ. of Southern California, Los Angeles, CA
    4.3sA Self-adjusting Scheme to Determine the Optimum RBB by Monitoring Leakage Currents
  Speaker(s): Nikhil Jayakumar - Texas A&M Univ., College Station, TX
  Author(s): Nikhil Jayakumar - Texas A&M Univ., College Station, TX
Sandeep Dhar - National Semiconductor Corp., Longmont, CO
Sunil Khatri - Texas A&M Univ., College Station, TX
    4.4sEnhanced Leakage Reduction Technique by Gate Replacement
  Speaker(s): Lin Yuan - Univ. of Maryland, College Park, MD
  Author(s): Lin Yuan - Univ. of Maryland, College Park, MD
Gang Qu - Univ. of Maryland, College Park, MD