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THURSDAY, June 16, 2005, 8:30 AM - 10:00 AM | Room: 208AB
TOPIC AREA:  DESIGN FOR MANUFACTURING (tools)

   SESSION 40
  Circuit Performance Under Parameter Variation
  Chair: L. Miguel Silveira - INESC-ID/IST/Cadence Labs, Lisbon, Portugal
  Organizers: Charlie Chung-Ping Chen, Joel Phillips

  

This session contains a variety of contributions motivated by circuit analysis under process variation. The first paper argues that in practical applications, adequate statistical analysis of timing can be performed with relatively simple path-based methods. The second paper surveys variability modeling for circuit applications. The final paper discusses sensitivity analysis in the context of power grid modeling.

    40.1   Statistical Static Timing Analysis: How Simple Can We Get?
  Speaker(s): Chirayu S. Amin - Northwestern Univ., Evanston, IL
  Author(s): Chirayu S. Amin - Northwestern Univ., Evanston, IL
Noel Menezes - Intel Corp., Hillsboro, OR
Kip Killpack - Intel Corp., Hillsboro, OR
Florentin Dartu - Intel Corp., Hillsboro, OR
Yehea Ismail - Northwestern Univ., Evanston, IL
Umakanta Choudhury - Intel Corp., Hillsboro, OR
Nagib Hakim - Intel Corp., Hillsboro, OR
    40.2Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach
  Speaker(s): Yu Cao - Arizona State Univ., Tempe, AZ
  Author(s): Yu Cao - Arizona State Univ., Tempe, AZ
Lawrence T. Clark - Arizona State Univ., Tempe, AZ
    40.3Power Grid Simulation Via Efficient Sampling-Based Sensitivity Analysis and Hierarchical Symbolic Relaxation
  Speaker(s): Peng Li - Texas A&M Univ., College Station, TX
  Author(s): Peng Li - Texas A&M Univ., College Station, TX