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| THURSDAY, June 16, 2005, 10:30 AM - 12:00 PM | Room: 207ABC | ||
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TOPIC AREA: SYSTEM-LEVEL DESIGN AND VERIFICATION (methods) | ||
| SESSION 41 | |||
| Special Session: Formally Verifying Your 10-Million Gate Design | |||
| Chair: Robert Damiano - Synopsys, Inc., Hillsboro, OR | |||
| Organizers: Pei-Hsin Ho | |||
| In this special session verification practitioners from IBM, nVIDIA and STMicroelectronics share their best known methods and success stories of employing formal property verification to achieve better design quality and shorter design cycle. | |||
 41.1 |
Formal Verification: Is It Real Enough? |
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| Speaker(s): | Yaron Wolfsthal - IBM Corp., Haifa, Israel | ||
| Author(s): | Yaron Wolfsthal - IBM Corp., Haifa, Israel Rebecca M. Gott - IBM Corp., Poughkeepsi, NY | ||
| 41.2 | Can We Really Do Without the Support of Formal Methods in the Verification of Large Designs? | ||
| Speaker(s): | Umberto Rossi - STMicroelectronics, Milano, Italy | ||
| Author(s): | Umberto Rossi - STMicroelectronics, Milano, Italy | ||
| 41.3 | Streamline Verification Process with Formal Property Verification to Meet Highly Compressed Design Cycle | ||
| Speaker(s): | Prosenjit Chattterjee - NVIDIA Corp., Santa Clara, CA | ||
| Author(s): | Prosenjit Chattterjee - NVIDIA Corp., Santa Clara, CA | ||
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