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| THURSDAY, June 16, 2005, 10:30 AM - 12:00 PM | Room: 210AB | ||
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TOPIC AREA: POWER (methods) | ||
| SESSION 43 | |||
| Power Estimation and Design Tradeoffs | |||
| Chair: Kimiyoshi Usami - Shibaura Institute of Technology, Saitama, Japan | |||
| Organizers: Jerry Frenkil, Amitava Majumdar | |||
| This session contains papers that address low power design at several levels. The first paper describes a novel and fast power estimation using hardware emulation. The second paper explores tradeoffs in power and performance in configurable processors. Power control in a network processor using clock gating is decribed in the third paper. The fourth paper presents a technique that overcomes delay variation by bulk voltage control. | |||
 43.1 |
Power Emulation: A New Paradigm for Power Estimation |
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| Speaker(s): | Joel D. Coburn - NEC-Labs America, Princeton, NJ | ||
| Author(s): | Joel D. Coburn - NEC-Labs America, Princeton, NJ Srivaths Ravi - NEC-Labs America, Princeton, NJ Anand Raghunathan - NEC-Labs America, Princeton, NJ | ||
| 43.2 | Implementing Low-Power Configurable Processors - Practical Options and Tradeoffs | ||
| Speaker(s): | Ashish Dixit - Tensilica, Inc., Santa Clara, CA | ||
| Author(s): | John H. Wei - Tensilica, Inc., Santa Clara, CA Chris Rowen - Tensilica, Inc., Santa Clara, CA | ||
| 43.3s | Low Power Network Processor Design Using Clock Gating | ||
| Speaker(s): | Yan Luo - Univ. of California, Riverside, CA | ||
| Author(s): | Yan Luo - Univ. of California, Riverside, CA Jia Yu - Univ. of California, Riverside, CA Jun Yang - Univ. of California, Riverside, CA Laxmi Bhuyan - Univ. of California, Riverside, CA | ||
| 43.4s | A Variation-Tolerant Sub-Threshold Design Approach | ||
| Speaker(s): | Nikhil Jayakumar - Texas A&M Univ., College Station, TX | ||
| Author(s): | Nikhil Jayakumar - Texas A&M Univ., College Station, TX Sunil Khatri - Texas A&M Univ., College Station, TX | ||
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