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| THURSDAY, June 16, 2005, 10:30 AM - 12:00 PM | Room: 209AB | ||
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TOPIC AREA: LOGIC DESIGN AND TEST (tools) | ||
| SESSION 44 | |||
| Programmable Architectures | |||
| Chair: Pedro Diniz - USC Information Sciences Institute, Marina Del Rey, CA | |||
| Organizers: Ryan Kastner, Steven Teig | |||
| The exploration of programmable architectures, particularly for low power, is an active area of contemporary research. This session addresses three distinct topics: power management, dynamic reconfiguration, and IP mapping. | |||
 44.1 |
Leakage Efficient Chip-Level Dual-Vdd Assignment with Time Slack Allocation for FPGA Power Reduction |
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| Speaker(s): | Yan Lin - Univ. of California, Los Angeles, CA | ||
| Author(s): | Yan Lin - Univ. of California, Los Angeles, CA Lei He - Univ. of California, Los Angeles, CA | ||
| 44.2 | Logic Block Clustering of Large Designs for Channel Width Constrained FPGAs | ||
| Speaker(s): | Marvin Tom - Univ. of British Columbia, Vancouver, BC, Canada | ||
| Author(s): | Marvin Tom - Univ. of British Columbia, Vancouver, BC, Canada Guy Lemieux - Univ. of British Columbia, Vancouver, BC, Canada | ||
| 44.3 | Dynamic Reconfiguration with Binary Translation: Breaking the ILP barrier with Software Compatibility | ||
| Speaker(s): | Antonio Carlos S. Beck Filho - UFRGS, Porto Alegre, Brazil | ||
| Author(s): | Antonio Carlos S. Beck Filho - UFRGS, Porto Alegre, Brazil Luigi Carro - UFRGS, Porto Alegre, Brazil | ||
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