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THURSDAY, June 16, 2005, 2:00 PM - 4:00 PM | Room: 208AB
TOPIC AREA:  LOGIC DESIGN AND TEST (mixed tools and methods)

   SESSION 50
  Testing for Process- and Timing-Related Faults
  Chair: Nicola Nicolici - McMaster University, Hamilton, Canada
  Organizers: Gordon Roberts, Kazumi Hatayama

  This session considers the impact of process variations and defects on various test algorithms and techniques, such as path delay test compaction, digital-to-analog converter type tests, memory tests and transient fault type tests.

    50.1   Path Delay Test Compaction with Process Variation Tolerance
  Speaker(s): Xiaoqing Wen - Kyushu Institute of Tech., Iizuka, Japan
  Author(s): Seiji Kajihara - Kyushu Institute of Tech., Iizuka, Japan
Masayasu Fukunaga - Kyushu Institute of Tech., Iizuka, Japan
Xiaoqing Wen - Kyushu Institute of Tech., Iizuka, Japan
Toshiyuki Maeda - STARC, Yokohama, Japan
Shuji Hamada - STARC, Yokohama, Japan
Yasuo Sato - STARC, Yokohama, Japan
    50.2A DFT Approach for Diagnosis and Process Variation-Aware Structural Test of Thermometer Coded Current Steering DACs
  Speaker(s): Rasit O. Topaloglu - Univ. of California at San Diego, La Jolla, CA
  Author(s): Rasit O. Topaloglu - Univ. of California at San Diego, La Jolla, CA
Alex Orailoglu - Univ. of California at San Diego, La Jolla, CA
    50.3Resistive-Open Defect Injection in SRAM Core-Cell: Analysis and Comparison between 0.13 µm and 90 nm Technologies
  Speaker(s): Patrick Girard - LIRMM, Montpellier, France
  Author(s): Luigi Dilillo - LIRMM, Montpellier, France
Patrick Girard - LIRMM, Montpellier, France
Serge Pravossoudovitch - LIRMM, Montpellier, France
Arnaud Virazel - LIRMM, Montpellier, France
Magali Bastian Hage-Hassan - Infineon Tech., Sophia-Antipolis, France
    50.4Asynchronous Circuits Transient Faults Sensitivity Evaluation
  Speaker(s): Yannick Monnet - TIMA Lab., Grenoble , France
  Author(s): Yannick Monnet - TIMA Lab., Grenoble, France
Marc Renaudin - TIMA Lab., Grenoble, France
Regis Leveugle - TIMA Lab., Grenoble, France