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| THURSDAY, June 16, 2005, 4:30 PM - 6:00 PM | Room: 210CD | ||
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TOPIC AREA: SYSTEM-LEVEL DESIGN AND VERIFICATION (methods) | ||
| SESSION 52 | |||
| PANEL: Platform ASIC Apprentices: Who Will Survive Your Boardroom? | |||
| Chair: Ron Wilson - EE Times, San Mateo, CA | |||
| Organizers: Joe Gianelli | |||
| Moore's law delivers higher performance and lower cost for FPGAs and ASICs alike, but at the 90 nm process node and below, design schedules using the traditional cell-based ASIC design methodology hit a wall of uncertainty. At 90 nm and below an emerging alternative, or apprentice, ASIC design platform is either Platform ASIC or FPGAs. Which alternative will survive your board room? | |||
 52.1 |
PANEL: Platform ASIC Apprentices: Who Will Survive Your Board Room? |
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| Speaker(s): | Christopher L. Hamlin - LSI Logic Corp., Milpitas, CA Ivo Bolsens - Xilinx, Inc., San Jose, CA Richard Tobias - Toshiba Corp., San Jose, CA Ken McElvain - Synplicity, Inc., Sunnyvale, CA Raul Camposano - Synopsys, Inc., Mountain View, CA Steve Leibson - Tensilica, Inc., Santa Clara, CA | ||
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