 |
 |
 |
 |
 |
 |
 |
|
|
|
| TUESDAY, June 14, 2005, 2:00 PM - 4:00 PM | Room: 209AB | ||
|
TOPIC AREA: LOGIC DESIGN AND TEST (mixed tools and methods) | ||
| SESSION 9 | |||
| Advances in Design-for-Testability Methods | |||
| Chair: Tom Williams - Synopsys, Inc., Boulder, CO | |||
| Organizers: Erik Jan Marinissen, Patrick Girard | |||
| This session presents novel scan-based techniques that improve test quality, reduce test costs, and ensure secure testable ICs. | |||
 9.1 |
Response Compression with Unlimited Number of Unknowns Using a New LFSR Architecture |
||
| Speaker(s): | Erik H. Volkerink - Agilent Technologies, Inc., San Jose, CA | ||
| Author(s): | Erik H. Volkerink - Agilent Technologies, Inc., San Jose, CA Subhasish Mitra - Intel Corp., Folsom, CA | ||
| 9.2 | Multi-Frequency Wrapper Design and Optimization for Embedded Cores Under Average Power Constraints | ||
| Speaker(s): | Qiang Xu - McMaster Univ., Hamilton, Canada | ||
| Author(s): | Qiang Xu - McMaster Univ., Hamilton, Canada Nicola Nicolici - McMaster Univ., Hamilton, Canada Krishnendu Chakrabarty - Duke Univ., Durham, NC | ||
| 9.3 | N-Detection Under Transparent-Scan | ||
| Speaker(s): | Irith Pomeranz - Purdue Univ., West Lafayette, IN | ||
| Author(s): | Irith Pomeranz - Purdue Univ., West Lafayette, IN | ||
| 9.4 | Secure Scan: A Design-for-Test Architecture for Crypto Chips | ||
| Speaker(s): | Bo Yang - Polytechnic Univ., Brooklyn, NY | ||
| Author(s): | Bo Yang - Polytechnic Univ., Brooklyn, NY Kaijie Wu - Univ. of Illinois, Chicago, IL Ramesh Karri - Polytechnic Univ., Brooklyn, NY | ||
 | |||