This tutorial is an overview of how predictive development can improve the efficiency, cycle time, robustness and predictability of IC design. By closing at the RT level, designers can be sure that their chosen micro-architecture is not only optimized to meet external system requirements, but can be smoothly and efficiently implemented through logic and physical design while meeting timing, power, test, area and routing constraints.

The tutorial covers the basic synthesis-driven design methodology from planning to final place and route, describing data requirements at each handoff point. Predictive development is then discussed and described using relevant examples to illustrate how downstream issues in timing, power and test are identified and resolved in the source RTL. Using the practical techniques that we will show, designers will understand how they can achieve closure at the RT level. With these techniques augmenting today's industry-standard physical synthesis implementation flows, and with a deterministic path from RTL to final STA, the long-held goal of RTL handoff is within our reach.